CY3125R62

CY3125R62 Datasheet

CY3125

Part	Datasheet
CY3125R62	CY3125R62 (pdf)

PDF Datasheet Preview
CY3125 CPLD Development Tool for UNIX • VHDL IEEE 1076 and 1164 and Verilog IEEE 1364 high-level language compilers with the following features Designs are portable across multiple devices and/or EDA environments Facilitates the use of industry-standard simulation and synthesis tools for board and system-level design Support for functions and libraries facilitating modular design methodology • IEEE Standard 1076 and 1164 VHDL synthesis supports Enumerated types Operator overloading For... Generate statements Integers • IEEE Standard 1364 Verilog synthesis supports: Reduction and conditional operators Blocking and non-blocking procedural assignments While loops Integers • Several design entry methods support high-level and low-level design descriptions Behavioral VHDL and Verilog IF...THEN...ELSE; CASE... Boolean Structural Verilog and VHDL Designs can include multiple entry methods but only one HDL language in a single design. • UltraGen Synthesis and Fitting Technology Infers “modules” such as adders, comparators, etc., from behavioral descriptions and replaces them with circuits pre-optimized for the target device. User-selectable speed and/or area optimization on a block-by-block basis Perfect communication between synthesis and fitting Automatic selection of optimal flip-flop type D type/T type Automatic pin assignment • Supports for the following Cypress Programmable Logic Devices PSI Programmable Serial Interface Delta39K CPLDs Quantum38K CPLDs Ultra37000 CPLDs FLASH370i CPLDs MAX340 CPLDs Industry-standard PLDs 16V8, 20V8, 22V10 • VHDL and Verilog timing model output for use with third-party simulators • Static Timing Report: Provides timing information for any path broken down by the different steps of the path • Architecture Explorer and Dynamic Timing Analysis for PSI, Delta39K and Quantum38K devices: Graphical representation of exactly how your design will be implemented on your specific target device Zoom from the device level down to the macrocell level Determine the timing for any path and view that path on a graphical representation of the chip • Workstation support for Sun Solaris • On-line documentation and help Functional Description VHDL Verilog Product Ordering Information Product Code CY3125R62 Warp development system for UNIX CY3125 Warp includes • CD-ROM with Warp and on-line documentation Getting Started Manual, User’s Guide, HDL Reference Manual • VHDL for Programmable Logic Textbook • Registration Card Warp Enterprise, UltraGen, Ultra37000, Quantum38K, Delta39K, PSI, Programmable Serial Interface, MAX340, ISR, In-System Reprogrammable, and FLASH370i are trademarks of Cypress Semiconductor Corporation. Warp is a registered trademark of Cypress Semiconductor Corporation. Solaris is a trademark of Sun Microsystems Corporation. Active-HDL is a trademark of Aldec Incorporated. Page 7 of 8 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Document Title CY3125 CPLD Development Tool for UNIX Document Number 38-03046 Issue ECN NO. Date Orig. of Change Description of Change 109903 09/22/01 SZV Change from Spec number 38-01033 to 38-03046 111243 01/22/02 CNH Update product code CY3125 Page 8 of 8

PDF Datasheet Preview

CY3125

CPLD Development Tool for UNIX
• VHDL IEEE 1076 and 1164 and Verilog IEEE 1364 high-level language compilers with the following features Designs are portable across multiple devices and/or EDA environments

Facilitates the use of industry-standard simulation and synthesis tools for board and system-level design

Support for functions and libraries facilitating modular design methodology
• IEEE Standard 1076 and 1164 VHDL synthesis supports Enumerated types

Operator overloading

For... Generate statements

Integers
• IEEE Standard 1364 Verilog synthesis supports:

Reduction and conditional operators

Blocking and non-blocking procedural assignments

While loops

Integers
• Several design entry methods support high-level and
low-level design descriptions Behavioral VHDL and Verilog IF...THEN...ELSE;

CASE...

Boolean

Structural Verilog and VHDL

Designs can include multiple entry methods but only one HDL language in a single design.
• UltraGen Synthesis and Fitting Technology Infers “modules” such as adders, comparators, etc., from behavioral descriptions and replaces them with circuits pre-optimized for the target device.

User-selectable speed and/or area optimization on a block-by-block basis

Perfect communication between synthesis and fitting

Automatic selection of optimal flip-flop type D type/T type

Automatic pin assignment
• Supports for the following Cypress Programmable

Logic Devices PSI Programmable Serial Interface

Delta39K CPLDs

Quantum38K CPLDs

Ultra37000 CPLDs

FLASH370i CPLDs

MAX340 CPLDs

Industry-standard PLDs 16V8, 20V8, 22V10
• VHDL and Verilog timing model output for use with third-party simulators
• Static Timing Report:

Provides timing information for any path broken down by the different steps of the path
• Architecture Explorer and Dynamic Timing Analysis for PSI, Delta39K and Quantum38K devices:

Graphical representation of exactly how your design will be implemented on your specific target device

Zoom from the device level down to the macrocell level

Determine the timing for any path and view that path on a graphical representation of the chip
• Workstation support for Sun Solaris
• On-line documentation and help

Functional Description

VHDL

Verilog
Product Ordering Information

Product Code

CY3125R62 Warp development system for UNIX

CY3125

Warp includes
• CD-ROM with Warp and on-line documentation Getting

Started Manual, User’s Guide, HDL Reference Manual
• VHDL for Programmable Logic Textbook
• Registration Card

Warp Enterprise, UltraGen, Ultra37000, Quantum38K, Delta39K, PSI, Programmable Serial Interface, MAX340, ISR, In-System Reprogrammable, and FLASH370i are trademarks of Cypress Semiconductor Corporation. Warp is a registered trademark of Cypress Semiconductor Corporation. Solaris is a trademark of Sun Microsystems Corporation. Active-HDL is a trademark of Aldec Incorporated.

Page 7 of 8

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

Document Title CY3125 CPLD Development Tool for UNIX Document Number 38-03046

Issue ECN NO. Date

Orig. of Change Description of Change
109903 09/22/01 SZV

Change from Spec number 38-01033 to 38-03046
111243 01/22/02 CNH

Update product code

CY3125

Page 8 of 8

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Datasheet ID: CY3125R62 507770