CY2VC511ZXCT

CY2VC511ZXCT Datasheet

CY2VC511

Part	Datasheet
CY2VC511ZXCT	CY2VC511ZXCT (pdf)

Related Parts	Information
CY2VC511ZXC	CY2VC511ZXC

PDF Datasheet Preview
CY2VC511 27 MHz Clock Generator with VCXO • Generates 27 MHz Output Clock • Uses 27 MHz LVCMOS Reference Clock • LVCMOS Output • VCXO with 230 ppm Minimum Pull Range • Fully Integrated Low Noise Phase Locked Loop PLL • Linear Voltage-to-Frequency Control Curve • Supply Voltage 3.3V • Pb-free 16-Pin TSSOP Package The CY2VC511 is a PLL based clock generator with VCXO control. It takes a low swing 27 MHz reference clock, and generates an adjustable 27 MHz output clock. The device has a single LVCMOS output and operates from a 3.3V power supply. The VIN pin is an analog input that enables the user to pull the output frequency. The pullability range is at least 230 ppm ±115 ppm . The pull curve is very linear. Unlike conventional VCXO designs, the output frequency adjustment is achieved by a proprietary PLL design. This permits the use of 27 MHz clock reference. Logic Block Diagram REFIN LOW -NOISE PLL • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback CY2VC511 Pinout Figure Pin Diagram - 16-Pin TSSOP REFIN Table Pin Definitions - 16-Pin TSSOP Pin 1 9 Name REFIN Type 1.8V CMOS Input Analog Input 13 11, 16 5, 6, 10, 12, 14 2, 3, 4 7, 8, 15 CLK DNU NC VDD VSS CMOS Output Power Description Reference Clock Input VCXO Control Voltage - VIN has a positive control slope that is, increasing the voltage on VIN causes the output frequency to increase The nominal output frequency is determined when VIN = 1.65V 27 MHz Output Clock Do Not Use DNU pins are electrically connected, but perform no function No Connect NC pins are not connected to the die Supply Voltage 3.3V Ground Page 2 of 7 [+] Feedback CY2VC511 Frequency Table Input Reference Frequency MHz PLL Multiplier Value 1 Output Frequency MHz 27 VCXO and VIN The output frequency of the device is adjusted over a limited range by use of the VCXO feature. This feature is typically used to phase and frequency lock to a separate reference clock. The frequency is controlled by the analog voltage on the VIN pin. The nominal output frequency is generated when VIN = 1.65V. As the voltage on VIN is increased, the output frequency increases. The voltage range for VIN is from 0V VSS to VDD. The relationship between output frequency ppm to VIN voltage is very linear over a large portion of the control voltage range. Application Information Power Supply Filtering Techniques As in any high speed analog circuitry, noise on the power supply pins can degrade device performance. For general power plane decoupling, make certain there is at least one tantalum capacitor ~5 to 10 uF in the general vicinity of this device. Additionally, ensure there is one or two multi-layer ceramic chip capacitors or uF located as close as possible to the power and ground pins of the device. Ensure the layout is optimized to minimize power and ground inductance and locate the capacitor as close to the device pins as possible. Absolute Maximum Conditions Parameter VDD VIN[1] TS TJ ESDHBM ΘJA[2] Supply Voltage Input Voltage, DC Temperature, Storage Temperature, Junction ESD Protection Human Body Model Flammability Rating Thermal Resistance, Junction to Ambient Condition Relative to VSS Non operating JEDEC STD 22-A114-B At 1/8 in 0 m/s airflow 1 m/s airflow m/s airflow Ordering Information Part Number Pb-Free CY2VC511ZXC CY2VC511ZXCT Package Description 16-Pin TSSOP 16-Pin TSSOP - Tape and Reel Package Drawings and Dimensions Figure 16-Pin TSSOP mm Body CY2VC511 Product Flow Commercial, 0° to 70°C Commercial, 0° to 70°C 51-85091 B Page 5 of 7 [+] Feedback CY2VC511 Document History Page Document Title CY2VC511 27 MHz Clock Generator with VCXO Document Number 001-10796 ECN No. Orig. of Submission Change Description of Change 506248 See ECN New data sheet A 1285703 JWK/KVM/ See ECN Changed definition of nominal frequency to VIN = 1.65V Added CLOAD specification Changed RUP value Corrected TR/TF conditions and specification Removed pull down resistor on SEL Updated several drawings Edited data sheet for template compliance B 2705638 XHT/KVM/ 05/13/2009 Changed title from Low Noise Clock Generator with VCXO to 27 MHz Clock AESA Generator with VCXO, Basic configuration change Reference changed from crystal to driven clock, Output changed from 216 MHz to 27 MHz, Pinout changed to show no connects, Pin 11 changed to DNU, VDD range changed from ±0.2V to ±5%, Thermal resistance data added, IOL & IOH changed from 2mA to 4mA Phase noise specs removed, IIVIN changed from 10uA to 60uA, Rise & fall times changed, IDD changed C 2768029 *D 2905106 09/18/2009 05/14/10 Remove reference to OE/PD# pin in IDD spec Change parameter name IIVIN to IVIN Change parameter LIN to INLVIN, add note to definition Add max limit for TR, TF ns Change TLOCK max from 10 ms to 5 ms Updated package diagram. Page 6 of 7 [+] Feedback CY2VC511 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.

PDF Datasheet Preview

CY2VC511
27 MHz Clock Generator with VCXO
• Generates 27 MHz Output Clock
• Uses 27 MHz LVCMOS Reference Clock
• LVCMOS Output
• VCXO with 230 ppm Minimum Pull Range
• Fully Integrated Low Noise Phase Locked Loop PLL
• Linear Voltage-to-Frequency Control Curve
• Supply Voltage 3.3V
• Pb-free 16-Pin TSSOP Package

The CY2VC511 is a PLL based clock generator with VCXO control. It takes a low swing 27 MHz reference clock, and generates an adjustable 27 MHz output clock. The device has a single LVCMOS output and operates from a 3.3V power supply.

The VIN pin is an analog input that enables the user to pull the output frequency. The pullability range is at least 230 ppm ±115 ppm . The pull curve is very linear.

Unlike conventional VCXO designs, the output frequency adjustment is achieved by a proprietary PLL design. This permits the use of 27 MHz clock reference.

Logic Block Diagram

REFIN

LOW -NOISE PLL
• San Jose, CA 95134-1709
• 408-943-2600
[+] Feedback

CY2VC511

Pinout

Figure Pin Diagram - 16-Pin TSSOP

REFIN

Table Pin Definitions - 16-Pin TSSOP

Pin 1 9

Name REFIN

Type 1.8V CMOS Input Analog Input
13 11, 16 5, 6, 10, 12, 14 2, 3, 4 7, 8, 15

CLK DNU NC VDD VSS

CMOS Output Power

Description Reference Clock Input VCXO Control Voltage - VIN has a positive control slope that is, increasing the voltage on VIN causes the output frequency to increase The nominal output frequency is determined when VIN = 1.65V 27 MHz Output Clock Do Not Use DNU pins are electrically connected, but perform no function No Connect NC pins are not connected to the die Supply Voltage 3.3V Ground

Page 2 of 7 [+] Feedback

CY2VC511

Frequency Table

Input Reference Frequency MHz

PLL Multiplier Value 1

Output Frequency MHz 27

VCXO and VIN

The output frequency of the device is adjusted over a limited range by use of the VCXO feature. This feature is typically used to phase and frequency lock to a separate reference clock. The frequency is controlled by the analog voltage on the VIN pin. The nominal output frequency is generated when VIN = 1.65V. As the voltage on VIN is increased, the output frequency increases. The voltage range for VIN is from 0V VSS to VDD. The relationship between output frequency ppm to VIN voltage is very linear over a large portion of the control voltage range.

Application Information

Power Supply Filtering Techniques

As in any high speed analog circuitry, noise on the power supply pins can degrade device performance. For general power plane decoupling, make certain there is at least one tantalum capacitor ~5 to 10 uF in the general vicinity of this device. Additionally, ensure there is one or two multi-layer ceramic chip capacitors or uF located as close as possible to the power and ground pins of the device. Ensure the layout is optimized to minimize power and ground inductance and locate the capacitor as close to the device pins as possible.

Absolute Maximum Conditions

Parameter

VDD VIN[1] TS TJ ESDHBM ΘJA[2]

Supply Voltage Input Voltage, DC Temperature, Storage Temperature, Junction ESD Protection Human Body Model Flammability Rating Thermal Resistance, Junction to Ambient

Condition

Relative to VSS Non operating

JEDEC STD 22-A114-B At 1/8 in 0 m/s airflow 1 m/s airflow m/s airflow
Ordering Information

Part Number Pb-Free CY2VC511ZXC CY2VC511ZXCT

Package Description
16-Pin TSSOP 16-Pin TSSOP - Tape and Reel

Package Drawings and Dimensions

Figure 16-Pin TSSOP mm Body

CY2VC511

Product Flow Commercial, 0° to 70°C Commercial, 0° to 70°C
51-85091 *B

Page 5 of 7 [+] Feedback

CY2VC511

Document History Page

Document Title CY2VC511 27 MHz Clock Generator with VCXO Document Number 001-10796

ECN No.

Orig. of Submission

Change

Description of Change
506248

See ECN New data sheet
*A 1285703 JWK/KVM/ See ECN Changed definition of nominal frequency to VIN = 1.65V

Added CLOAD specification

Changed RUP value

Corrected TR/TF conditions and specification

Removed pull down resistor on SEL

Updated several drawings

Edited data sheet for template compliance
*B 2705638 XHT/KVM/ 05/13/2009 Changed title from Low Noise Clock Generator with VCXO to 27 MHz Clock

AESA

Generator with VCXO, Basic configuration change Reference changed from
crystal to driven clock, Output changed from 216 MHz to 27 MHz, Pinout changed
to show no connects, Pin 11 changed to DNU, VDD range changed from ±0.2V to ±5%, Thermal resistance data added, IOL & IOH changed from 2mA to 4mA

Phase noise specs removed, IIVIN changed from 10uA to 60uA, Rise & fall times
changed, IDD changed
*C 2768029 *D 2905106
09/18/2009 05/14/10

Remove reference to OE/PD# pin in IDD spec Change parameter name IIVIN to IVIN Change parameter LIN to INLVIN, add note to definition Add max limit for TR, TF ns Change TLOCK max from 10 ms to 5 ms Updated package diagram.

Page 6 of 7 [+] Feedback

CY2VC511

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY2VC511ZXCT Datasheet file may be downloaded here without warranties.

Datasheet ID: CY2VC511ZXCT 507754