CY29775AXI

CY29775AXI Datasheet

CY29775

Part	Datasheet
CY29775AXI	CY29775AXI (pdf)

Related Parts	Information
CY29775AXIT	CY29775AXIT

PDF Datasheet Preview
CY29775 2.5V or 3.3V, 200-MHz, 14 Output Zero Delay Buffer • Output frequency range MHz to 200 MHz • Input frequency range MHz to 125 MHz • 2.5V or 3.3V operation • Split 2.5V/3.3V outputs • 14 Clock outputs Drive up to 28 clock lines • 1 Feedback clock output • 2 LVCMOS reference clock inputs • 150 ps max output-output skew • PLL bypass mode • Spread Aware • Output enable/disable • Industrial temperature range to +85°C • 52-Pin 1.0-mm TQFP package The CY29775 is a low-voltage high-performance 200-MHz PLL-based zero delay buffer designed for high-speed clock distribution applications. The CY29775 features two reference clock inputs and provides 14 outputs partitioned in 3 banks of 5, 5, and 4 outputs. Bank A and Bank B divide the VCO output by 4 or 8 while Bank C divides by 8 or 12 per SEL A:C settings, see Function Table Bank A, B, and C on page These dividers allow output to input ratios of 6:1, 4:1, 3:1, 2:1, 3:2, 4:3, 1:1, and Each LVCMOS compatible output can drive 50Ω series or parallel terminated transmission lines. For series terminated transmission lines, each output can drive one or two traces giving the device an effective fanout of The PLL is ensured stable given that the VCO is configured to run between 200 MHz to 500 MHz. This allows a wide range of output frequencies from MHz to 200 MHz. For normal operation, the external feedback input, FB_IN, is connected to the feedback output, FB_OUT. The internal VCO is running at multiples of the input reference clock set by the feedback divider, see Frequency Table on page When PLL_EN is LOW, PLL is bypassed and the reference clock directly feeds the output dividers. This mode is fully static and the minimum input clock frequency specification does not apply. Block Diagram V C O _ S E L 1 ,0 PLL_EN TCLK_SEL TCLK0 TCLK1 F B _ IN SELA SELB SELC CLK_STP# FB_SEL 1,0 M R #/O E PLL 200 500MHz ÷2 / ÷4 CLK STOP ÷2 / ÷4 CLK STOP ÷4 / ÷6 CLK STOP ÷4 / ÷6 / ÷8 / ÷12 QA0 QA1 QA2 QA3 QA4 QB0 QB1 QB2 QB3 QB4 QC0 QC1 QC2 QC3 FB_OUT • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback Pinouts Figure Pin Diagram - 52-Pin 1.0-mm TQFP package CY29775 QB0 VDDQB NC VSS QC3 VDDQC QC2 VSS QC1 VDDQC QC0 VSS VCO_SEL0 V SS MR#/OE CLK_STP# SELB SELC PLL_EN SELA TCLK_SEL TCLK0 TCLK1 V CO_SEL1 V DD A V DD 52 51 50 49 48 47 46 45 44 43 42 41 40 7 C Y29775 33 14 15 16 17 18 19 20 21 22 23 24 25 26 V SS QB1 V DDQB QB2 V SS QB3 V DDQB QB4 FB_IN V SS FB_OUT V DDFB NC VDDQA QA0 VSS QA1 VDDQA QA2 FB_SEL1 VSS QA3 VDDQA QA4 AVSS FB_SEL0 Table Pin Definition - 52-Pin 1.0-mm TQFP package Ordering Information Part Number CY29775AI CY29775AIT Pb-free CY29775AXI CY29775AXIT Package Type 52-pin TQFP 52-pin TQFP -Tape and Reel 52-pin TQFP 52-pin TQFP -Tape and Reel Product Flow Industrial, to +85°C Industrial, to 85°C Status Obsolete Industrial, to +85°C Industrial, to 85°C Active Package Drawing and Dimension Figure 52-Lead Thin Plastic Quad Flat Pack 10 x 10 x mm A52B 51-85158-** Page 10 of 11 [+] Feedback CY29775 Document History Page Document Title:CY29775 2.5V or 3.3V, 200-MHz, 14 Output Zero Delay Buffer Document # 38-07480 ECN No. Issue Date Orig. of Change Description of Change 125955 04/29/03 RGL New Data Sheet 1875214 See ECN WWZ/AESA Added Pb-free part numbers and updated device status Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Page 11 of 11 Spread Aware is a trademark of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback

PDF Datasheet Preview

CY29775
2.5V or 3.3V, 200-MHz, 14 Output Zero Delay Buffer
• Output frequency range MHz to 200 MHz
• Input frequency range MHz to 125 MHz
• 2.5V or 3.3V operation
• Split 2.5V/3.3V outputs
• 14 Clock outputs Drive up to 28 clock lines
• 1 Feedback clock output
• 2 LVCMOS reference clock inputs
• 150 ps max output-output skew
• PLL bypass mode
• Spread Aware
• Output enable/disable
• Industrial temperature range to +85°C
• 52-Pin 1.0-mm TQFP package

The CY29775 is a low-voltage high-performance 200-MHz PLL-based zero delay buffer designed for high-speed clock distribution applications.

The CY29775 features two reference clock inputs and provides 14 outputs partitioned in 3 banks of 5, 5, and 4 outputs. Bank A and Bank B divide the VCO output by 4 or 8 while Bank C divides by 8 or 12 per SEL A:C settings, see Function Table Bank A, B, and C on page These dividers allow output to input ratios of 6:1, 4:1, 3:1, 2:1, 3:2, 4:3, 1:1, and Each LVCMOS compatible output can drive 50Ω series or parallel terminated transmission lines. For series terminated transmission lines, each output can drive one or two traces giving the device an effective fanout of

The PLL is ensured stable given that the VCO is configured to run between 200 MHz to 500 MHz. This allows a wide range of output frequencies from MHz to 200 MHz. For normal operation, the external feedback input, FB_IN, is connected to the feedback output, FB_OUT. The internal VCO is running at multiples of the input reference clock set by the feedback divider, see Frequency Table on page

When PLL_EN is LOW, PLL is bypassed and the reference clock directly feeds the output dividers. This mode is fully static and the minimum input clock frequency specification does not apply.

Block Diagram

V C O _ S E L 1 ,0 PLL_EN

TCLK_SEL TCLK0 TCLK1 F B _ IN SELA

SELB

SELC CLK_STP#

FB_SEL 1,0 M R #/O E

PLL 200 500MHz
÷2 / ÷4

CLK STOP
÷2 / ÷4

CLK STOP
÷4 / ÷6

CLK STOP
÷4 / ÷6 / ÷8 / ÷12

QA0 QA1 QA2 QA3 QA4

QB0 QB1 QB2 QB3 QB4

QC0 QC1 QC2 QC3

FB_OUT
• San Jose, CA 95134-1709
• 408-943-2600
[+] Feedback

Pinouts

Figure Pin Diagram - 52-Pin 1.0-mm TQFP package

CY29775

QB0 VDDQB

NC VSS QC3 VDDQC QC2 VSS QC1 VDDQC QC0 VSS VCO_SEL0

V SS MR#/OE CLK_STP#

SELB SELC PLL_EN SELA TCLK_SEL TCLK0 TCLK1 V CO_SEL1

V DD A V DD
52 51 50 49 48 47 46 45 44 43 42 41 40
7 C Y29775 33
14 15 16 17 18 19 20 21 22 23 24 25 26

V SS QB1 V DDQB QB2 V SS QB3 V DDQB QB4 FB_IN V SS FB_OUT V DDFB NC

VDDQA QA0 VSS QA1 VDDQA QA2 FB_SEL1 VSS QA3 VDDQA QA4 AVSS FB_SEL0

Table Pin Definition - 52-Pin 1.0-mm TQFP package
Ordering Information

Part Number CY29775AI CY29775AIT Pb-free CY29775AXI CY29775AXIT

Package Type 52-pin TQFP 52-pin TQFP -Tape and Reel
52-pin TQFP 52-pin TQFP -Tape and Reel

Product Flow Industrial, to +85°C Industrial, to 85°C

Status Obsolete

Industrial, to +85°C Industrial, to 85°C

Active

Package Drawing and Dimension

Figure 52-Lead Thin Plastic Quad Flat Pack 10 x 10 x mm A52B
51-85158-**

Page 10 of 11 [+] Feedback

CY29775

Document History Page

Document Title:CY29775 2.5V or 3.3V, 200-MHz, 14 Output Zero Delay Buffer Document # 38-07480

ECN No. Issue Date

Orig. of Change

Description of Change
125955 04/29/03

RGL New Data Sheet
1875214 See ECN WWZ/AESA Added Pb-free part numbers and updated device status

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Page 11 of 11

Spread Aware is a trademark of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders.
[+] Feedback

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Datasheet ID: CY29775AXI 507742