CY23S08SXC-1

CY23S08SXC-1 Datasheet

CY23S08

Part	Datasheet
CY23S08SXC-1	CY23S08SXC-1 (pdf)

Related Parts	Information
CY23S08SXC-2T	CY23S08SXC-2T
CY23S08SXC-1T	CY23S08SXC-1T
CY23S08SXI-2T	CY23S08SXI-2T
CY23S08SXI-2	CY23S08SXI-2
CY23S08SXC-4T	CY23S08SXC-4T
CY23S08SXC-4	CY23S08SXC-4
CY23S08SXC-2	CY23S08SXC-2
CY23S08SXI-4	CY23S08SXI-4
CY23S08SXI-4T	CY23S08SXI-4T
CY23S08SXC-2H	CY23S08SXC-2H
CY23S08SXC-2HT	CY23S08SXC-2HT

PDF Datasheet Preview
CY23S08 3.3V Zero Delay Buffer • Zero Input Output Propagation Delay, adjustable by Capacitive Load on FBK input • Multiple configurations see Table 3 on page 3 • Multiple Low-skew Outputs 45 ps Typical Output-output skew Two banks of four Outputs, three-stateable by two select Inputs • 10 MHz to 140 MHz Operating Range • 65 ps Typical Cycle-to-cycle Jitter • Advanced um CMOS Technology • Space saving 16-pin, SOIC and TSSOP Packages • 3.3V Operation • Spread Aware Functional Description The CY23S08 is a 3.3V zero delay buffer designed to distribute high speed clocks in PC, workstation, datacom, telecom, and other high performance applications. The part has an on-chip PLL which locks to an input clock presented on the REF pin. The PLL feedback must be driven into the FBK pin, and obtained from one of the outputs. The input-to-output propagation delay is less than 350 ps, and output-to-output skew is less than 250 ps. The CY23S08 has two banks of four outputs each, which can be controlled by the Select inputs as shown in Table 2 on page If all output clocks are not required, Bank B can be three-stated. The select inputs also enable the input clock to be directly applied to the output for chip and system testing purposes. The CY23S08 PLL enters a power down state when there are no rising edges on the REF input. In this mode, all outputs are three-stated and the PLL is turned off, resulting in less than 50 uA of current draw. The PLL shuts down in two additional cases as shown in Table 2 on page Multiple CY23S08 devices accept the same input clock and distribute it in a system. In this case, the skew between the outputs of two devices is less than 700 ps. The CY23S08 is available in five different configurations, as shown in Table 3 on page The is the base part, where the output frequencies equal the reference if there is no counter in the feedback path. The is the high drive version of the and rise and fall times on this device are much faster. The enables you to obtain 2X and 1X frequencies on each output bank. The exact configuration and output frequencies depends on which output drives the feedback pin. The is the high drive version of the and rise and fall times on this device are much faster. The enables you to obtain 2X clocks on all outputs. Thus, the part is versatile, and can be used in a variety of applications. Logic Block Diagram Extra Divider Select Input Decoding Extra Divider FBK CLKA1 CLKA2 CLKA3 CLKA4 CLKB1 CLKB2 CLKB3 CLKB4 • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback Pinouts Table Pin Definition Signal REF[1] CLKA1[2] CLKA2[2] CLKB1[2] CLKB2[2] S2[3] S1[3] CLKB3[2] CLKB4[2] CLKA3[2] Ordering Information Ordering Code Pb-free CY23S08ZXC-1H CY23S08ZXC-1HT CY23S08SXC-4 CY23S08SXC-4T CY23S08SXI-4 CY23S08SXI-4T Package Type 16-pin 150-mil SOIC 16-pin 150-mil and Reel 16-pin 150-mil SOIC 16-pin 150-mil and Reel 16-pin 4.4mm TSSOP 16-pin 4.4mm TSSOP 16-pin 150-mil SOIC 16-pin 150-mil and Reel 16-pin 150-mil SOIC 16-pin 150-mil and Reel 16-pin 150-mil SOIC 16-pin 150-mil and Reel 16-pin 150-mil SOIC 16-pin 150-mil and Reel 16-pin 150-mil SOIC 16-pin 150-mil and Reel CY23S08 Operating Range Commercial 0° to 70°C Commercial 0° to 70°C Industrial to 85°C Industrial to 85°C Commercial 0° to 70°C Commercial 0° to 70°C Commercial 0° to 70°C Commercial 0° to 70°C Commercial 0° to 70°C Commercial 0° to 70°C Industrial to 85°C Industrial to 85°C Commercial 0° to 70°C Commercial 0° to 70°C Industrial to 85°C Industrial to 85°C Page 8 of 11 [+] Feedback CY23S08 Package Drawings and Dimensions Figure 16-Pin 150-Mil SOIC S16 PIN 1 ID DIMENSIONS IN INCHES[MM] MIN. REFERENCE JEDEC MS-012 PACKAGE WEIGHT 0.15gms PART # S16.15 STANDARD PKG. SZ16.15 LEAD FREE PKG. MAX. SEATING PLANE 0° ~8° X 45° 51-85068-B Figure 16-Pin Thin Shrunk Small Outline Package mm Body Z16 PIN 1 ID BSC. MAX. SEATING PLANE GAUGE PLANE 0° -8° 51-85091-A Page 9 of 11 [+] Feedback CY23S08 Document History Page Document Title CY23S08 3.3V Zero Delay Buffer Document Number 38-07265 Orig. of Submission Change Description of Change 110530 12/02/01 Change from Spec number 38-01107 to 38-07265 122863 12/20/02 Added power up requirements to operating conditions information. 130951 1442823 WWZ/AESA See ECN Updated ordering info with status update. Added new Pb-free part numbers. 2600345 WWZ/PYRS 11/03/08 Updated max frequency number from 133 MHz to 140 MHz on page 1 and page 4 load capacitance description 2658081 KVM/PYRS 02/16/09 Corrected TSSOP package size from 150 mil to mm in Ordering Infor- mation Table. Removed references to SOIC in the pinout drawing and pin description table on page Added CY23S08ZXC-1HT to the Ordering Information Table. Updated Ordering Information Table to remove obsolete devices. Removed Status column. 2761988 09/10/09 Added industrial temperature range to Operating Conditions table. Added numerical values to Operating Range column of Ordering Information table. Removed references to device. Page 10 of 11 [+] Feedback CY23S08 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers Wireless Memories Image Sensors psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. All products and company names mentioned in this document may be the trademarks of their respective holders. Page 11 of 11 [+] Feedback

PDF Datasheet Preview

CY23S08
3.3V Zero Delay Buffer
• Zero Input Output Propagation Delay, adjustable by Capacitive Load on FBK input
• Multiple configurations see Table 3 on page 3
• Multiple Low-skew Outputs 45 ps Typical Output-output skew Two banks of four Outputs, three-stateable by two select Inputs
• 10 MHz to 140 MHz Operating Range
• 65 ps Typical Cycle-to-cycle Jitter
• Advanced um CMOS Technology
• Space saving 16-pin, SOIC and TSSOP Packages
• 3.3V Operation
• Spread Aware

Functional Description

The CY23S08 is a 3.3V zero delay buffer designed to distribute high speed clocks in PC, workstation, datacom, telecom, and other high performance applications. The part has an on-chip PLL which locks to an input clock presented on the REF pin. The PLL feedback must be driven into the FBK pin, and obtained from one of the outputs. The input-to-output propagation delay is less than 350 ps, and output-to-output skew is less than 250 ps.

The CY23S08 has two banks of four outputs each, which can be controlled by the Select inputs as shown in Table 2 on page If all output clocks are not required, Bank B can be three-stated. The select inputs also enable the input clock to be directly applied to the output for chip and system testing purposes.

The CY23S08 PLL enters a power down state when there are no rising edges on the REF input. In this mode, all outputs are three-stated and the PLL is turned off, resulting in less than 50 uA of current draw. The PLL shuts down in two additional cases as shown in Table 2 on page

Multiple CY23S08 devices accept the same input clock and distribute it in a system. In this case, the skew between the outputs of two devices is less than 700 ps.

The CY23S08 is available in five different configurations, as shown in Table 3 on page The is the base part, where the output frequencies equal the reference if there is no counter in the feedback path. The is the high drive version of the and rise and fall times on this device are much faster.

The enables you to obtain 2X and 1X frequencies on each output bank. The exact configuration and output frequencies depends on which output drives the feedback pin. The is the high drive version of the and rise and fall times on this device are much faster.

The enables you to obtain 2X clocks on all outputs. Thus, the part is versatile, and can be used in a variety of applications.

Logic Block Diagram

Extra Divider

Select Input

Decoding

Extra Divider

FBK CLKA1 CLKA2 CLKA3 CLKA4

CLKB1 CLKB2 CLKB3 CLKB4
• San Jose, CA 95134-1709
• 408-943-2600
[+] Feedback

Pinouts

Table Pin Definition

Signal

REF[1]

CLKA1[2]

CLKA2[2]

CLKB1[2]

CLKB2[2]

S2[3]

S1[3]

CLKB3[2]

CLKB4[2]

CLKA3[2]
Ordering Information
Ordering Code Pb-free CY23S08ZXC-1H CY23S08ZXC-1HT CY23S08SXC-4 CY23S08SXC-4T CY23S08SXI-4 CY23S08SXI-4T

Package Type
16-pin 150-mil SOIC 16-pin 150-mil and Reel 16-pin 150-mil SOIC 16-pin 150-mil and Reel 16-pin 4.4mm TSSOP 16-pin 4.4mm TSSOP 16-pin 150-mil SOIC 16-pin 150-mil and Reel 16-pin 150-mil SOIC 16-pin 150-mil and Reel 16-pin 150-mil SOIC 16-pin 150-mil and Reel 16-pin 150-mil SOIC 16-pin 150-mil and Reel 16-pin 150-mil SOIC 16-pin 150-mil and Reel

CY23S08

Operating Range

Commercial 0° to 70°C Commercial 0° to 70°C Industrial to 85°C Industrial to 85°C Commercial 0° to 70°C Commercial 0° to 70°C Commercial 0° to 70°C Commercial 0° to 70°C Commercial 0° to 70°C Commercial 0° to 70°C Industrial to 85°C Industrial to 85°C Commercial 0° to 70°C Commercial 0° to 70°C Industrial to 85°C Industrial to 85°C

Page 8 of 11 [+] Feedback

CY23S08

Package Drawings and Dimensions

Figure 16-Pin 150-Mil SOIC S16

PIN 1 ID

DIMENSIONS IN INCHES[MM] MIN.

REFERENCE JEDEC MS-012

PACKAGE WEIGHT 0.15gms PART #

S16.15 STANDARD PKG.

SZ16.15 LEAD FREE PKG.

MAX.

SEATING PLANE
0° ~8°

X 45°
51-85068-*B

Figure 16-Pin Thin Shrunk Small Outline Package mm Body Z16

PIN 1 ID

BSC.

MAX.

SEATING PLANE

GAUGE PLANE
0° -8°
51-85091-*A

Page 9 of 11 [+] Feedback

CY23S08

Document History Page

Document Title CY23S08 3.3V Zero Delay Buffer Document Number 38-07265

Orig. of Submission

Change

Description of Change
110530
12/02/01 Change from Spec number 38-01107 to 38-07265
122863
12/20/02 Added power up requirements to operating conditions information.
130951
1442823 WWZ/AESA See ECN Updated ordering info with status update. Added new Pb-free part numbers.
2600345 WWZ/PYRS 11/03/08 Updated max frequency number from 133 MHz to 140 MHz on page 1 and page
4 load capacitance description
2658081 KVM/PYRS 02/16/09 Corrected TSSOP package size from 150 mil to mm in Ordering Infor-
mation Table. Removed references to SOIC in the pinout drawing and pin
description table on page
Added CY23S08ZXC-1HT to the Ordering Information Table.
Updated Ordering Information Table to remove obsolete devices. Removed

Status column.
2761988
09/10/09
Added industrial temperature range to Operating Conditions table. Added numerical values to Operating Range column of Ordering Information table. Removed references to device.

Page 10 of 11 [+] Feedback

CY23S08

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales.

Products PSoC Clocks & Buffers Wireless Memories Image Sensors
psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

All products and company names mentioned in this document may be the trademarks of their respective holders.

Page 11 of 11
[+] Feedback

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY23S08SXC-1 Datasheet file may be downloaded here without warranties.

Datasheet ID: CY23S08SXC-1 507692