CY23FS04ZXI-3T

CY23FS04ZXI-3T Datasheet

CY23FS04-3

Part	Datasheet
CY23FS04ZXI-3T	CY23FS04ZXI-3T (pdf)

Related Parts	Information
CY23FS04ZXI-3	CY23FS04ZXI-3

PDF Datasheet Preview
CY23FS04-3 Failsafe V/3.3 V Zero Delay Buffer • Internal digital controlled crystal oscillator DCXO for continuous glitch-free operation • Zero input-output propagation delay • Low-jitter 35 ps max RMS outputs • Low output-to-output skew 200 ps max • MHz to MHz reference input • Supports industry standard input crystals • MHz outputs • 5V-tolerant inputs • Phase-locked loop PLL bypass mode • Dual reference inputs • 16-Pin thin shrunk small outline package TSSOP • V or V output power supplies • V core power supply • Industrial temperature range Logic Block Diagram XIN XOUT REFSEL DCXO REF1 REF2 FailsafeTM Block S[2:1] Decoder 2 Functional Description The CY23FS04-3 is a FailSafe zero delay buffer with two reference clock inputs and four phase-aligned outputs. The device provides an optimum solution for applications where continuous operation is required in the event of a primary clock failure. The continuous, glitch-free operation is achieved by using a DCXO, which serves as a redundant clock source in the event of a reference clock failure by maintaining the last frequency and phase information of the reference clock. The unique feature of the CY23FS04-3 is that the DCXO is in fact the primary clocking source, which is synchronized phase-aligned to the external reference clock. When this external clock is restored, the DCXO automatically resynchronizes to the external clock. The frequency of the crystal that is connected to the DCXO must be an integer factor of the frequency of the reference clock. This factor is set by two select lines S[2:1], see Table The output power supply VDD can be connected to either V or V. VDDC is the power supply pin for internal circuits and must be connected to V. 2 CLKA[2:1] CLKB[2:1] FAIL# /SAFE • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback CY23FS04-3 Contents Pin Configuration 3 FailSafe 4 XTAL Selection Criteria and Application Example 7 Absolute Maximum 9 Recommended Pullable Crystal Specifications 9 Operating Conditions for FailSafe Devices.................... 9 Electrical Characteristics for FailSafe Devices 10 Switching Characteristics for FailSafe Devices 10 Ordering 11 Ordering Code 11 Package 12 Acronyms 12 Document Conventions 12 Units of Measure 12 Document History Page 13 Sales, Solutions, and Legal Information 13 Worldwide Sales and Design Support....................... 13 Products 13 PSoC Solutions 13 Page 2 of 13 [+] Feedback Pin Configuration Figure Pin Diagram - CY23FS04-3 16-Pin TSSOP CY23FS04-3 Table Pin Definition Pin No. 2, 1 4, 3 13, 14 15 5, 12 8 9 10 11 7 6 16 Pin Name REF[2:1] CLKB[2:1] CLKA[2:1] FBK S[2:1] XIN XOUT FAIL#/SAFE VDD VDDC VSS REFSEL Description Reference clock inputs. 5V-tolerant.[4] Bank B clock outputs.[1,2] Bank A clock outputs.[1,2] Feedback input to the PLL.[1,4] Frequency select pins and PLL and DCXO bypass mode.[3] Reference crystal input. Reference crystal output. Valid reference indicator. A high level indicates a valid reference input. 2.5-V or 3.3-V power supply. 3.3-V power supply. Ground. Reference select. Selects the active reference clock from either REF1 or REF2. REFSEL = 1, REF1 is selected REFSEL = 0, REF2 is selected. Table Configuration Table S[2:1] 00 01 10 11 XTAL MHz REF MHz OUT MHz REF:OUT Ratio PLL and DCXO Bypass Mode REF:XTAL Ratio 1/2 6 Out:XTAL Ratio 1/2 6 Notes For normal operation, connect either one of the four clock outputs to the FBK input. Weak pull downs on all outputs. Weak pull ups on these inputs. Weak pull down on these inputs Page 3 of 13 [+] Feedback CY23FS04-3 FailSafe Function The CY23FS04-3 is targeted at clock distribution applications that require continued operation should the main reference clock fail. Existing approaches to this requirement have used multiple reference clocks with either internal or external methods for switching between references. The problem with this technique is that it leads to interruptions or glitches when transitioning from one reference to another, often requiring complex external circuitry or software to maintain system stability. The technique implemented in this design completely eliminates any switching of references to the PLL, greatly simplifying system design. The CY23FS04-3 PLL is driven by the crystal oscillator, which is phase-aligned to an external reference clock so that the output of the device is effectively phase-aligned to the reference via the external feedback loop. This is accomplished by using a digitally controlled capacitor array to pull the crystal frequency over an approximate range of +300 ppm from its nominal frequency. In this mode, if the reference frequency fails stop or disappear , the DCXO maintains its last setting and a flag signal FAIL#/SAFE is set to indicate failure of the reference clock. The CY23FS04-3 provides two select bits, S1 and S2, to control the reference-to-crystal frequency ratio. The DCXO is internally tuned to the phase and frequency of the external reference only when the reference frequency divided by this ratio is within the DCXO capture range. If the frequency is out of range, a flag is set on the FAIL#/SAFE pin notifying the system that the selected reference is not valid. If the reference moves in range, then the flag is cleared, indicating to the system that the selected reference is valid. Figure Fail#/Safe Timing for Input Reference Failing Catastrophically REF OUT Fail#/Safe Ordering Information Part Number Pb-free CY23FS04ZXI-3 CY23FS04ZXI-3T Ordering Code Definition CY23FS04 ZX I 3 T Package Type 16-Pin TSSOP 16-Pin TSSOP Tape and Reel CY23FS04-3 Product Flow Industrial, °C to 85 °C Industrial, °C to 85 °C Package type T = tape and reel, blank = tube Configuration specific identification code Temperature code I = Industrial Package 16-pin TSSOP, Pb-free Device number Notes iicnppuhtadseelaoyffsisegt uinacrlaundteesedjittfeorr.a maximum 4:1 input edge ratio between the two signals as long as tSR I is maintained. Static phase Parameters guaranteed by design and characterization, not 100% tested in production. Page 11 of 13 [+] Feedback Package Diagram Figure 16-Pin TSSOP mm Body CY23FS04-3 Acronyms Acronym DCXO digitally controlled crystal oscillator electrostatic discharge phase locked loop root mean square SSOP shrunk small outline package XTAL crystal 51-85091 *C Document Conventions Units of Measure Symbol °C µA mA ms MHz ns pF ps V Unit of Measure degree Celsius micro amperes milli amperes milli seconds Mega Hertz nano seconds pico Farad pico seconds Volts Page 12 of 13 [+] Feedback CY23FS04-3 Document History Page Document Title CY23FS04-3 Failsafe V/3.3 V Zero Delay Buffer Document Number 001-59002 ECN No. Submission Date Orig. of Change Description of Change 2865337 01/25/2010 CXQ New spec release. 2925613 04/30/10 KVM Posting to external web. Added Acronyms, Document Conventions, and Ordering Code Definition Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 \| PSoC 3 \| PSoC 5 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Page 13 of 13 FailSafe is a trademark of Cypress Semiconductor Corporation. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors. All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback

PDF Datasheet Preview

CY23FS04-3

Failsafe V/3.3 V Zero Delay Buffer
• Internal digital controlled crystal oscillator DCXO for continuous glitch-free operation
• Zero input-output propagation delay
• Low-jitter 35 ps max RMS outputs
• Low output-to-output skew 200 ps max
• MHz to MHz reference input
• Supports industry standard input crystals
• MHz outputs
• 5V-tolerant inputs
• Phase-locked loop PLL bypass mode
• Dual reference inputs
• 16-Pin thin shrunk small outline package TSSOP
• V or V output power supplies
• V core power supply
• Industrial temperature range

Logic Block Diagram

XIN XOUT

REFSEL

DCXO

REF1 REF2

FailsafeTM Block

S[2:1]

Decoder 2

Functional Description

The CY23FS04-3 is a FailSafe zero delay buffer with two reference clock inputs and four phase-aligned outputs. The device provides an optimum solution for applications where continuous operation is required in the event of a primary clock failure.

The continuous, glitch-free operation is achieved by using a DCXO, which serves as a redundant clock source in the event of a reference clock failure by maintaining the last frequency and phase information of the reference clock.

The unique feature of the CY23FS04-3 is that the DCXO is in fact the primary clocking source, which is synchronized phase-aligned to the external reference clock. When this external clock is restored, the DCXO automatically resynchronizes to the external clock.

The frequency of the crystal that is connected to the DCXO must be an integer factor of the frequency of the reference clock. This factor is set by two select lines S[2:1], see Table The output power supply VDD can be connected to either V or V. VDDC is the power supply pin for internal circuits and must be connected to V.
2 CLKA[2:1]

CLKB[2:1]

FAIL# /SAFE
• San Jose, CA 95134-1709
• 408-943-2600
[+] Feedback

CY23FS04-3

Contents

Pin Configuration 3 FailSafe 4
XTAL Selection Criteria and Application Example 7 Absolute Maximum 9 Recommended Pullable Crystal Specifications 9 Operating Conditions for FailSafe Devices.................... 9 Electrical Characteristics for FailSafe Devices 10 Switching Characteristics for FailSafe Devices 10 Ordering 11
Ordering Code 11

Package 12 Acronyms 12 Document Conventions 12

Units of Measure 12 Document History Page 13 Sales, Solutions, and Legal Information 13

Worldwide Sales and Design Support....................... 13 Products 13 PSoC Solutions 13

Page 2 of 13 [+] Feedback

Pin Configuration

Figure Pin Diagram - CY23FS04-3 16-Pin TSSOP

CY23FS04-3

Table Pin Definition

Pin No. 2, 1 4, 3 13, 14 15 5, 12 8 9 10 11 7 6 16

Pin Name REF[2:1] CLKB[2:1] CLKA[2:1] FBK S[2:1] XIN XOUT FAIL#/SAFE VDD VDDC VSS REFSEL

Description Reference clock inputs. 5V-tolerant.[4] Bank B clock outputs.[1,2] Bank A clock outputs.[1,2] Feedback input to the PLL.[1,4] Frequency select pins and PLL and DCXO bypass mode.[3]

Reference crystal input.

Reference crystal output.

Valid reference indicator. A high level indicates a valid reference input.
2.5-V or 3.3-V power supply.
3.3-V power supply.

Ground.

Reference select. Selects the active reference clock from either REF1 or REF2. REFSEL = 1, REF1 is selected REFSEL = 0, REF2 is selected.

Table Configuration Table

S[2:1]
00 01 10 11

XTAL MHz

REF MHz

OUT MHz

REF:OUT Ratio

PLL and DCXO Bypass Mode

REF:XTAL Ratio
1/2 6

Out:XTAL Ratio
1/2 6

Notes For normal operation, connect either one of the four clock outputs to the FBK input. Weak pull downs on all outputs. Weak pull ups on these inputs. Weak pull down on these inputs

Page 3 of 13 [+] Feedback

CY23FS04-3

FailSafe Function

The CY23FS04-3 is targeted at clock distribution applications that require continued operation should the main reference clock fail. Existing approaches to this requirement have used multiple reference clocks with either internal or external methods for switching between references. The problem with this technique is that it leads to interruptions or glitches when transitioning from one reference to another, often requiring complex external circuitry or software to maintain system stability. The technique implemented in this design completely eliminates any switching of references to the PLL, greatly simplifying system design.

The CY23FS04-3 PLL is driven by the crystal oscillator, which is phase-aligned to an external reference clock so that the output of the device is effectively phase-aligned to the reference via the external feedback loop. This is accomplished by using a digitally controlled capacitor array to pull the crystal frequency over an approximate range of +300 ppm from its nominal frequency.

In this mode, if the reference frequency fails stop or disappear , the DCXO maintains its last setting and a flag signal FAIL#/SAFE is set to indicate failure of the reference clock.

The CY23FS04-3 provides two select bits, S1 and S2, to control the reference-to-crystal frequency ratio. The DCXO is internally tuned to the phase and frequency of the external reference only when the reference frequency divided by this ratio is within the DCXO capture range. If the frequency is out of range, a flag is set on the FAIL#/SAFE pin notifying the system that the selected reference is not valid. If the reference moves in range, then the flag is cleared, indicating to the system that the selected reference is valid.

Figure Fail#/Safe Timing for Input Reference Failing Catastrophically

REF OUT Fail#/Safe
Ordering Information

Part Number Pb-free CY23FS04ZXI-3 CY23FS04ZXI-3T
Ordering Code Definition CY23FS04 ZX I 3 T

Package Type
16-Pin TSSOP 16-Pin TSSOP Tape and Reel

CY23FS04-3

Product Flow Industrial, °C to 85 °C Industrial, °C to 85 °C

Package type T = tape and reel, blank = tube Configuration specific identification code Temperature code I = Industrial Package 16-pin TSSOP, Pb-free Device number

Notes
iicnppuhtadseelaoyffsisegt uinacrlaundteesedjittfeorr.a maximum 4:1 input edge ratio between the two signals as long as tSR I is maintained. Static phase

Parameters guaranteed by design and characterization, not 100% tested in production.

Page 11 of 13
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Package Diagram

Figure 16-Pin TSSOP mm Body

CY23FS04-3

Acronyms

Acronym

DCXO digitally controlled crystal oscillator
electrostatic discharge
phase locked loop
root mean square

SSOP shrunk small outline package

XTAL
crystal
51-85091 *C

Document Conventions

Units of Measure

Symbol °C µA mA ms MHz ns pF ps V

Unit of Measure degree Celsius micro amperes milli amperes milli seconds Mega Hertz nano seconds pico Farad pico seconds Volts

Page 12 of 13
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CY23FS04-3

Document History Page

Document Title CY23FS04-3 Failsafe V/3.3 V Zero Delay Buffer Document Number 001-59002

ECN No.

Submission Date

Orig. of Change

Description of Change
2865337 01/25/2010

CXQ New spec release.
2925613 04/30/10

KVM Posting to external web.
Added Acronyms, Document Conventions, and Ordering Code Definition

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.

Products Automotive Clocks & Buffers Interface Lighting & Power Control

Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF
cypress.com/go/automotive cypress.com/go/clocks
cypress.com/go/interface cypress.com/go/powerpsoc
cypress.com/go/plc cypress.com/go/memory
cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB
cypress.com/go/wireless

PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Page 13 of 13

FailSafe is a trademark of Cypress Semiconductor Corporation. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors. All products and company names mentioned in this document may be the trademarks of their respective holders.
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Datasheet ID: CY23FS04ZXI-3T 507691