CTSLVEL16VRNLG

CTSLVEL16VRNLG Datasheet

CTSLVEL16VR

Part	Datasheet
CTSLVEL16VRNLG	CTSLVEL16VRNLG (pdf)

Related Parts	Information
CTSLVEL16VRNNG	CTSLVEL16VRNNG

PDF Datasheet Preview
CTSLVEL16VR PECL/ECL Oscillator Gain Stage & Buffer with Selectable Enable MLP8, MLP16  Minimizes External Components  Selectable Enable Polarity and Threshold CMOS or PECL  High Bandwidth for  Similar Operation as CTS100EL16  -147 dBc/Hz Typical Noise Floor BLOCK DIAGRAM The CTSLVEL16VR is a specialized oscillator gain stage with a high gain output buffer including an enable function. The HG outputs have voltage gain several times greater than the outputs. It provides a selectable HG enable that allows continuous oscillator operation via the outputs. The CTSLVEL16VR provides adjustable internal pull-down current sources for the outputs and optional 10mA current sources for the HG outputs. Internal input biasing further reduces the number of needed external components. ENGINEERING NOTES Functionality of MLP16 Package CTSLVEL16VRNLG The CTSLVEL16VRNLG provides a selectable HG enable that allows continuous oscillator operation via the outputs. Table 1 shows the operating modes. Leaving EN-SEL open NC selects PECL/ECL operation for the EN pad/pin. In this mode the HG outputs are enabled when EN is left open NC or set to a PECL/ECL low. Connecting EN-SEL to VCC, VEE or VBB selects CMOS operation for the EN pad/pin. When EN-SEL is tied to VEE, the HG outputs are disabled when EN is left open NC . When EN-SEL is tied to VCC or VBB, the HG outputs are enabled when EN is left open. This default logic condition can be overridden by a resistor connected to the opposite supply. The CTSLVEL16VRNLG also provides a VBB and internal bias resistors from D to VBB and to VBB. The VBB pin supports 1.5mA sink/source current. VBB should be bypassed to ground or VCC with a capacitor. Outputs each have a selectable on-chip pull-down current source. See Table 2 for the supported values. External resistors may also be used to increase pull-down current to a maximum total of 25mA for the outputs. Each of the HG outputs has an optional on-chip pull-down current source of 10mA. When pad/pin VEEP is left open NC , the output current sources are disabled and the QHG HG operate as standard PECL/ECL. When VEEP is connected to VEE, the current sources are activated. The QHG HG pull-down current can be decreased by using a resistor between VEEP and VEE. North Americas +1-800-757-6686 • International +1-508-435-6831 • Asia +65-655-17551 • Specifications are subject to change without notice. 1 CTSLVEL16VR PECL/ECL Oscillator Gain Stage & Buffer with Selectable Enable MLP8, MLP16 Table 1 - Enable Truth Table EN-SEL PECL Low, VEE or NC PECL High or VCC VEE1 CMOS Low, VEE or NC CMOS High or VCC VCC or VBB1,2 CMOS Low or VEE CMOS High, VCC or NC 1 EN-SEL connections must be Data 2 Date codes prior to 0428 do not support this operating mode. QHG Data Low Data Low Data HG Data High Data High Data Table 2 - Current Source Truth Table CS-SEL 4mA typ 4mA typ VEE1 8mA typ VCC1 1 Connection must be less than 8mA typ 4mA typ PART ORDERING INFORMATION Part Number CTSLVEL16VRNLG CTSLVEL16VRNNG Package MLP16 MLP8 Pin Configuration for CTSLVEL16VRNLG D1 VBB 2 EN 3 VEE 4 Leave Pad open or connect to VEE 8Q 7 VCC 6 QHG 5 QHG Pin Configuration for CTSLVEL16VRNNG Marking 100G 16R YYWW R5G YYWW North Americas +1-800-757-6686 • International +1-508-435-6831 • Asia +65-655-17551 • Specifications are subject to change without notice. 10 CTSLVEL16VR PECL/ECL Oscillator Gain Stage & Buffer with Selectable Enable MLP8, MLP16 PACKAGE DIMENSIONS North Americas +1-800-757-6686 • International +1-508-435-6831 • Asia +65-655-17551 • Specifications are subject to change without notice. 11

PDF Datasheet Preview

CTSLVEL16VR

PECL/ECL Oscillator Gain Stage & Buffer with Selectable Enable

MLP8, MLP16
 Minimizes External Components  Selectable Enable Polarity and

Threshold CMOS or PECL
 High Bandwidth for  Similar Operation as CTS100EL16  -147 dBc/Hz Typical Noise Floor

BLOCK DIAGRAM

The CTSLVEL16VR is a specialized oscillator gain stage with a high gain output buffer including an enable function. The HG outputs have voltage gain several times greater than the outputs. It provides a selectable HG enable that allows continuous oscillator operation via the outputs.

The CTSLVEL16VR provides adjustable internal pull-down current sources for the outputs and optional 10mA current sources for the HG outputs. Internal input biasing further reduces the number of needed external components.

ENGINEERING NOTES

Functionality of MLP16 Package CTSLVEL16VRNLG The CTSLVEL16VRNLG provides a selectable HG enable that allows continuous oscillator operation via the outputs. Table 1 shows the operating modes. Leaving EN-SEL open NC selects PECL/ECL operation for the EN pad/pin. In this mode the HG outputs are enabled when EN is left open NC or set to a PECL/ECL low.

Connecting EN-SEL to VCC, VEE or VBB selects CMOS operation for the EN pad/pin. When EN-SEL is tied to VEE, the HG outputs are disabled when EN is left open NC . When EN-SEL is tied to VCC or VBB, the HG outputs are enabled when EN is left open. This default logic condition can be overridden by a resistor connected to the opposite supply.

The CTSLVEL16VRNLG also provides a VBB and internal bias resistors from D to VBB and to VBB. The VBB pin supports 1.5mA sink/source current. VBB should be bypassed to ground or VCC with a capacitor.

Outputs each have a selectable on-chip pull-down current source. See Table 2 for the supported values. External resistors may also be used to increase pull-down current to a maximum total of 25mA for the outputs.

Each of the HG outputs has an optional on-chip pull-down current source of 10mA. When pad/pin VEEP is left open NC , the output current sources are disabled and the QHG HG operate as standard PECL/ECL. When VEEP is connected to VEE, the current sources are activated. The QHG HG pull-down current can be decreased by using a resistor between VEEP and VEE.

North Americas +1-800-757-6686
• International +1-508-435-6831
• Asia +65-655-17551
•

Specifications are subject to change without notice. 1

CTSLVEL16VR

PECL/ECL Oscillator Gain Stage & Buffer with Selectable Enable

MLP8, MLP16

Table 1 - Enable Truth Table

EN-SEL

PECL Low, VEE or NC PECL High or VCC

VEE1

CMOS Low, VEE or NC CMOS High or VCC

VCC or VBB1,2

CMOS Low or VEE CMOS High, VCC or NC
1 EN-SEL connections must be

Data
2 Date codes prior to 0428 do not support this operating mode.

QHG Data Low Data Low Data

HG Data High Data High Data

Table 2 - Current Source Truth Table

CS-SEL
4mA typ
4mA typ

VEE1
8mA typ

VCC1
1 Connection must be less than
8mA typ 4mA typ
PART ORDERING INFORMATION

Part Number CTSLVEL16VRNLG CTSLVEL16VRNNG

Package

MLP16 MLP8

Pin Configuration for CTSLVEL16VRNLG

D1 VBB 2 EN 3 VEE 4

Leave Pad open or
connect to VEE
8Q 7 VCC 6 QHG 5 QHG

Pin Configuration for CTSLVEL16VRNNG

Marking
100G 16R YYWW R5G YYWW

North Americas +1-800-757-6686
• International +1-508-435-6831
• Asia +65-655-17551
•

Specifications are subject to change without notice. 10

CTSLVEL16VR

PECL/ECL Oscillator Gain Stage & Buffer with Selectable Enable

MLP8, MLP16

PACKAGE DIMENSIONS

North Americas +1-800-757-6686
• International +1-508-435-6831
• Asia +65-655-17551
•

Specifications are subject to change without notice. 11

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CTSLVEL16VRNLG Datasheet file may be downloaded here without warranties.

Datasheet ID: CTSLVEL16VRNLG 507358