CTSLV310TG

CTSLV310TG Datasheet

CTSLV310

Part	Datasheet
CTSLV310TG	CTSLV310TG (pdf)

Related Parts	Information
CTSLV310QG	CTSLV310QG

PDF Datasheet Preview
CTSLV310 Ultra-Low Phase Noise LVPECL, LVDS Buffer and Translator SON8, MSOP8  2.5V-3.3V Operation  Ultra-Low Phase Noise Floor o LVPECL -167dBc/Hz o LVDS -165dBc/Hz  Configurable o LVPECL or LVDS Output o ÷1 or ÷2 o Enable Active High or Low  1GHz+ Bandwidth  RoHS Compliant Pb Free Packages BLOCK DIAGRAM  The CTSLV310 is a configurable LVPECL, LVDS buffer & translator IC that is optimized for ultra-low phase noise and 2.5V-3.3V nominal supply voltage. It is particularly useful in converting crystal or SAW based oscillators into LVPECL and LVDS outputs for up to 1GHz of bandwidth. For a design that includes gain in the signal path, refer to the CTSLV315.  A configurable IC design capable of providing LVPECL or LVDS outputs, ÷1 or ÷2 function, and active high or active low enable selection. See Table 1 for details of the configurations options that provide designers with a single IC buffer/translator solution that is extremely compact, flexible and high performance.  8 configurations which are determined by the static voltage levels of b-0 and b-1. Table 1 details the configurations. Table 1 - Possible IC Configuration Configuration Bits b-0 Open Low High b-1 Open Low High Open Low High Open Low High Functional Configuration Output Type LVPECL LVDS Not Used Enable Polarity Active High Active High Active Low Active Low Active High Active High Active Low Active Low Not Used Division ÷1 ÷2 ÷1 ÷2 ÷1 ÷2 ÷1 ÷2 Not Used North Americas +1-800-757-6686 • International +1-508-435-6831 • Asia +65-655-17551 • Specifications are subject to change without notice. 1 CTSLV310 Ultra-Low Phase Noise LVPECL, LVDS Buffer and Translator SON8, MSOP8 Input Termination The D input bias is VDD/2 fed through an internal resistor. For clock applications, an input signal of at least 750m VPP ensures the CTSLV10 meets AC specifications. The input should also be AC coupled to maintain a 50% duty cycle on the outputs. The input can be driven to any voltage between 0V and VDD without damage or waveform degradation. LVPECL Output Termination Techniques DC Coupling The LVPECL compatible output stage of the CTSLV310 uses a current drive topology to maximize switching speed as illustrated below. Two current source PMOS transistors M1-M2 feed the output pins. M5 is an NMOS current source which is switched by M3 and M4. When M4 is on, M5 takes current from M2. This produces an output current of 5.1mA low output state . M3 is off, and the entire 21.1mA flows through the output pin. The associated output voltage swings match LVPECL levels when external resistors terminate the outputs. Both Q and QN should always be terminated identically to avoid waveform distortion and circulating current caused by unsymmetrical loads. This rule should be followed even if only one output is in use. Output Stage Vbp M1 External Circuitry 21.1mA 21.1mA 21.1mA - High M4 5.1mA - Low M5 16mA VTT = VDD - 2.0V Typical Output Termination North Americas +1-800-757-6686 • International +1-508-435-6831 • Asia +65-655-17551 • Specifications are subject to change without notice. 2 PART ORDERING INFORMATION Part Number CTSLV310QG Package SON8 CTSLV310TG MSOP8 MSOP8 Marking SYW BE0G / YYWW North Americas +1-800-757-6686 • International +1-508-435-6831 • Asia +65-655-17551 • Specifications are subject to change without notice. 7 CTSLV310 Ultra-Low Phase Noise LVPECL, LVDS Buffer and Translator SON8, MSOP8 PACKAGE DIMENSIONS North Americas +1-800-757-6686 • International +1-508-435-6831 • Asia +65-655-17551 • Specifications are subject to change without notice. 8 CTSLV310 Ultra-Low Phase Noise LVPECL, LVDS Buffer and Translator SON8, MSOP8 North Americas +1-800-757-6686 • International +1-508-435-6831 • Asia +65-655-17551 • Specifications are subject to change without notice. 9

PDF Datasheet Preview

CTSLV310

Ultra-Low Phase Noise LVPECL, LVDS Buffer and Translator

SON8, MSOP8
 2.5V-3.3V Operation  Ultra-Low Phase Noise Floor
o LVPECL -167dBc/Hz o LVDS -165dBc/Hz  Configurable o LVPECL or LVDS Output o ÷1 or ÷2 o Enable Active High or Low  1GHz+ Bandwidth  RoHS Compliant Pb Free Packages

BLOCK DIAGRAM
 The CTSLV310 is a configurable LVPECL, LVDS buffer & translator IC that is optimized for ultra-low phase noise and 2.5V-3.3V nominal supply voltage. It is particularly useful in converting crystal or SAW based oscillators into LVPECL and LVDS outputs for up to 1GHz of bandwidth. For a design that includes gain in the signal path, refer to the CTSLV315.
 A configurable IC design capable of providing LVPECL or LVDS outputs, ÷1 or ÷2 function, and active high or active low enable selection. See Table 1 for details of the configurations options that provide designers with a single IC buffer/translator solution that is extremely compact, flexible and high performance.
 8 configurations which are determined by the static voltage levels of b-0 and b-1. Table 1 details the configurations.

Table 1 - Possible IC Configuration

Configuration Bits
b-0 Open Low High
b-1 Open Low High Open Low High Open Low High

Functional Configuration

Output Type LVPECL LVDS Not Used

Enable Polarity Active High Active High Active Low Active Low Active High Active High Active Low Active Low Not Used

Division ÷1 ÷2 ÷1 ÷2 ÷1 ÷2 ÷1 ÷2

Not Used

North Americas +1-800-757-6686
• International +1-508-435-6831
• Asia +65-655-17551
•

Specifications are subject to change without notice. 1

CTSLV310

Ultra-Low Phase Noise LVPECL, LVDS Buffer and Translator

SON8, MSOP8

Input Termination The D input bias is VDD/2 fed through an internal resistor. For clock applications, an input signal of at least 750m VPP ensures the CTSLV10 meets AC specifications. The input should also be AC coupled to maintain a 50% duty cycle on the outputs. The input can be driven to any voltage between 0V and VDD without damage or waveform degradation.

LVPECL Output Termination Techniques

DC Coupling The LVPECL compatible output stage of the CTSLV310 uses a current drive topology to maximize switching speed as illustrated below. Two current source PMOS transistors M1-M2 feed the output pins. M5 is an NMOS current source which is switched by M3 and M4. When M4 is on, M5 takes current from M2. This produces an output current of 5.1mA low output state . M3 is off, and the entire 21.1mA flows through the
output pin. The associated output voltage swings match LVPECL levels when external resistors terminate the outputs.

Both Q and QN should always be terminated identically to avoid waveform distortion and circulating current caused by unsymmetrical loads. This rule should be followed even if only one output is in use.

Output

Stage

Vbp M1

External Circuitry
21.1mA
21.1mA
21.1mA - High

M4 5.1mA - Low

M5 16mA

VTT = VDD - 2.0V

Typical Output Termination

North Americas +1-800-757-6686
• International +1-508-435-6831
• Asia +65-655-17551
•

Specifications are subject to change without notice. 2
PART ORDERING INFORMATION

Part Number CTSLV310QG

Package SON8

CTSLV310TG

MSOP8

MSOP8

Marking SYW

BE0G / YYWW

North Americas +1-800-757-6686
• International +1-508-435-6831
• Asia +65-655-17551
•

Specifications are subject to change without notice. 7

CTSLV310

Ultra-Low Phase Noise LVPECL, LVDS Buffer and Translator

SON8, MSOP8

PACKAGE DIMENSIONS

North Americas +1-800-757-6686
• International +1-508-435-6831
• Asia +65-655-17551
•

Specifications are subject to change without notice. 8

CTSLV310

Ultra-Low Phase Noise LVPECL, LVDS Buffer and Translator

SON8, MSOP8

North Americas +1-800-757-6686
• International +1-508-435-6831
• Asia +65-655-17551
•

Specifications are subject to change without notice. 9

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CTSLV310TG Datasheet file may be downloaded here without warranties.

Datasheet ID: CTSLV310TG 507349