EP9315 Data Sheet
Part | Datasheet |
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EP9315-CBZ | EP9315-CBZ (pdf) |
Related Parts | Information |
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EP9315-IBZ | EP9315-IBZ |
PDF Datasheet Preview |
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EP9315 Data Sheet • 200-MHz ARM920T Processor • 16-kbyte Instruction Cache • 16-kbyte Data Cache • CE-enabled MMU • 100-MHz System Bus • MaverickCrunch Math Engine • Floating Point, Integer, and Signal Processing Instructions • Optimized for digital music compression and decompression algorithms. • Hardware interlocks allow in-line coding. • MaverickKey IDs • 32-bit Unique ID can be used for DRM-compliant 128-bit random ID. • Integrated Peripheral Interfaces • 32-bit SDRAM Interface up to 4 Banks • 32/16-bit SRAM / FLASH / ROM • Serial EEPROM Interface • EIDE up to 2 devices • 1/10/100-Mbps Ethernet MAC • Three UARTs • Three-port USB Full-speed Host OHCI 12 Mbits per second • LCD and Raster Interface with Graphics Accelerator Enhanced Universal Platform System-on-Chip Processor • IrDA Interface • PCMCIA Interface • Touchscreen Interface with ADC • 8 x 8 Keypad Scanner • One Serial Peripheral Interface SPI Port • 6-channel or 2-channel Serial Audio Interface I2S • 2-channel, Low-cost Serial Audio Interface AC'97 • 2 High-resolution PWMs 16 bits each • Internal Peripherals • 12 Direct Memory Access DMA Channels • Real-time Clock with Software Trim • Dual PLL controls all clock domains. • Watchdog Timer • Two General-purpose 16-bit Timers • One General-purpose 32-bit Timer • One 40-bit Debug Timer • Interrupt Controller • Boot ROM • Package • 352-pin PBGA COMMUNICATIONS PORTS Serial Audio Interface 3 UARTs w/ IrDA 3 USB Hosts Ethernet MAC Peripheral Bus Clocks & Timers 12-channel DMA MaverickKeyTM Boot ROM MaverickCrunchTM ARM920T D-Cache I-Cache 16KB 16KB Bus Bridge Interrupts & GPIO Keypad & Touch Screen I/F Processor Bus EIDE I/F SRAM & Flash I/F PCMCIA Unified SDRAM I/F Video/LCD Controller Graphics Accelerator MEMORY AND STORAGE 2010 Cirrus Logic All Rights Reserved USER INTERFACE Mar ‘10 DS638F2 EP9315 Enhanced Universal Platform SOC Processor OVERVIEW The EP9315 is an ARM920T-based system-on-a-chip design with a large peripheral set targeted to a variety of applications: • Thin Client Computers for Business and Home • Internet Radio • Internet Access Devices • Industrial Computers • Specialized Terminals • Point-of-sale Terminals • Test and Measurement Equipment The ARM920T microprocessor core with separate 16-kbyte, 64-way set-associative instruction and data caches is augmented by the MaverickCrunch coprocessor, enabling high-speed floating point calculations. MaverickKey unique hardware programmed IDs are a solution to the growing concern over secure web content and commerce. With Internet security playing an important role in the delivery of digital media such as ORDERING INFORMATION DS638F2 2010 Cirrus Logic All Rights Reserved EP9315 Enhanced Universal Platform SOC Processor List of Figures Figure Timing Diagram Drawing Key 14 Figure SDRAM Load Mode Register Cycle Timing Measurement 15 Figure SDRAM Burst Read Cycle Timing Measurement 16 Figure SDRAM Burst Write Cycle Timing Measurement 17 Figure SDRAM Auto Refresh Cycle Timing Measurement 18 Figure Static Memory Single Word Read Cycle Timing Measurement 19 Figure Static Memory Single Word Write Cycle Timing Measurement 20 Figure Static Memory Multiple Word Read 8-bit Cycle Timing Measurement 21 Figure Static Memory Multiple Word Write 8-bit Cycle Timing Measurement 22 Figure Static Memory Multiple Word Read 16-bit Cycle Timing Measurement 23 Figure Static Memory Multiple Word Write 16-bit Cycle Timing Measurement 24 Figure Static Memory Burst Read Cycle Timing Measurement 25 Figure Static Memory Burst Write Cycle Timing Measurement 26 Figure Static Memory Single Read Wait Cycle Timing Measurement 27 Figure Static Memory Single Write Wait Cycle Timing Measurement 28 Figure Static Memory Turnaround Cycle Timing Measurement 29 Figure PCMCIA Read Cycle Timing Measurement 30 Figure PCMCIA Write Cycle Timing Measurement 31 Figure Register Transfer to/from Device 33 Figure PIO Data Transfer to/from Device 35 Figure Initiating an Ultra DMA data-in Burst 37 Figure Sustained Ultra DMA data-in Burst 38 Figure Host Pausing an Ultra DMA data-in Burst 38 Figure Device Terminating an Ultra DMA data-in Burst 39 Figure Host Terminating an Ultra DMA data-in Burst 40 Figure Initiating an Ultra DMA data-out Burst 41 Figure Sustained Ultra DMA data-out Burst 42 Figure Device Pausing an Ultra DMA data-out Burst 42 Figure Host Terminating an Ultra DMA data-out Burst 43 Figure Device Terminating an Ultra DMA data-out Burst 44 Figure Ethernet MAC Timing Measurement 46 Figure TI Single Transfer Timing Measurement 48 Figure Microwire Frame Format, Single Transfer 48 Figure SPI Format with SPH=1 Timing Measurement 49 Figure Inter-IC Sound I2S Timing Measurement 50 Figure AC ‘97 Configuration Timing Measurement 51 Figure LCD Timing Measurement 52 Figure ADC Transfer Function 53 Figure JTAG Timing Measurement 54 Figure 352 Pin PBGA Pin Diagram 55 Figure 352 PIN BGA PINOUT 57 2010 Cirrus Logic All Rights Reserved DS638F2 EP9315 Enhanced Universal Platform SOC Processor List of Tables Table A. Change History 2 Table B. General Purpose Memory Interface Pin Assignments 6 Table C. IDE Interface Pin Assignments 7 Table D. Ethernet Media Access Controller Pin Assignments 7 Table E. Audio Interfaces Pin Assignment 7 Table F. LCD Interface Pin Assignments 8 Table G. Touch Screen Interface with 12-bit Analog-to-Digital Converter Pin Assignments 8 Table H. 64-Key Keypad Interface Pin Assignments 8 Table I. Universal Asynchronous Receiver/Transmitters Pin Assignments 9 Table J. Triple Port USB Host Pin Assignments 9 Table K. Two-Wire Port with EEPROM Support Pin Assignments 9 Table L. Real-Time Clock with Pin Assignments 10 Table M.PLL and Clocking Pin Assignments 10 Table N. Interrupt Controller Pin Assignment 10 Table O. Dual LED Pin Assignments 10 Table P. General Purpose Input/Output Pin Assignment 11 Table Q. Reset and Power Management Pin Assignments 11 Table R. Hardware Debug Interface 11 Table S. PCMCIA Interface 11 Table R. 352 Pin Diagram Dimensions 56 Table S. Pin Descriptions 60 Table T. Pin Multiplex Usage Information 62 DS638F2 2010 Cirrus Logic All Rights Reserved EP9315 Enhanced Universal Platform SOC Processor Processor Core - ARM920T The ARM920T is a Harvard architecture processor with separate 16-kbyte instruction and data caches with an 8word line length but a unified memory. The processor utilizes a five-stage pipeline consisting of fetch, decode, execute, memory, and write stages. Key features include: • ARM 32-bit and Thumb 16-bit compressed Instruction Sets • 32-bit Advanced Micro-Controller Bus Architecture AMBA • 16-kbyte Instruction Cache with Lockdown • 16-kbyte Data Cache programmable write-through or write-back with Lockdown • MMU for CE and Other Operating Systems • Translation Look Aside Buffers with 64 Data and 64 Instruction Entries • Programmable Page Sizes of 1 Mbyte, 64 kbyte, 4 kbyte, and 1 kbyte • Independent Lockdown of TLB Entries MaverickCrunch Math Engine The MaverickCrunch Engine is a mixed-mode coprocessor designed primarily to accelerate the math processing required to rapidly encode digital audio formats. It accelerates single and double precision integer and floating point operations plus an integer multiply-accumulate MAC instruction that is considerably faster than the ARM920T's native MAC instruction. The ARM920T coprocessor interface is utilized thereby sharing its memory interface and instruction stream. Hardware forwarding and interlock allows the ARM to handle looping and addressing while MaverickCrunch handles computation. Features include: • IEEE-754 single and double precision floating point • 32 / 64-bit integer • Add / multiply / compare • Integer MAC 32-bit input with 72-bit accumulate • Integer Shifts • Floating point to/from integer conversion • Sixteen 64-bit register files • Four 72-bit accumulators MaverickKey Unique ID MaverickKey unique hardware programmed IDs are a solution to the growing concern over secure web content and commerce. With Internet security playing an important role in the delivery of digital media such as books or music, traditional software methods are quickly becoming unreliable. The MaverickKey unique IDs provide OEMs with a method of utilizing specific hardware IDs such as those assigned for SDMI Secure Digital Music Initiative or any other authentication mechanism. Both a specific 32-bit ID as well as a 128-bit random ID is programmed into the EP9315 through the use of laser probing technology. These IDs can then be used to match secure copyrighted content with the ID of the target device the EP9315 is powering, and then deliver the copyrighted information over a secure connection. In addition, secure transactions can benefit by also matching device IDs to server IDs. MaverickKey IDs provide a level of hardware security required for today’s Internet appliances. General Purpose Memory Interface SDRAM, SRAM, ROM, FLASH The EP9315 features a unified memory address model where all memory devices are accessed over a common address/data bus. A separate internal port is dedicated to the read-only Raster/LCD refresh engine, while the rest of the memory accesses are performed via the Processor bus. The SRAM memory controller supports 8, 16 and 32-bit devices and accommodates an internal boot ROM concurrently with 32-bit SDRAM memory. • 1-4 banks of 32-bit 66 or 100 MHz SDRAM • One internal port dedicated to the Raster/LCD Refresh Engine Read Only • Address and data bus shared between SDRAM, SRAM, ROM, and FLASH memory • NOR FLASH memory supported Table B. General Purpose Memory Interface Pin Assignments Pin Mnemonic Pin Description SDCLK SDCLKEN SDCSn[3:0] RASn CASn SDWEn CSn[7:6] and CSn[3:0] AD[25:0] DA[31:0] DQMn[3:0] WRn RDn WAITn SDRAM Clock SDRAM Clock Enable SDRAM Chip Selects 3-0 SDRAM RAS SDRAM CAS SDRAM Write Enable Chip Selects 7, 6, 3, 2, 1, 0 Address Bus 25-0 Data Bus 31-0 SDRAM Output Enables / Data Masks SRAM Write Strobe SRAM Read / OE Strobe SRAM Wait Input 2010 Cirrus Logic All Rights Reserved Ordering Information The order numbers for the device are: EP9315-CBZ EP9315-IBZ 0°C to +70°C -40°C to +85°C EP9315 CBZ 352-pin PBGA 352-pin PBGA Lead Free Lead Free Product Line Embedded Processor Lead Material Z = Lead Free Package Type B = 352-Ball, Plastic Ball Grid Array 27 mm x 27 mm Temperature Range C = Commercial Version E = Extended Operating Version I = Industrial Operating Version Note Go to the Cirrus Logic Internet site at to find contact information for your local sales representative. Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find one nearest you go to IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries "Cirrus" believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind express or implied . Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. 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IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, MaverickCrunch, MaverickKey, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. Microsoft and Windows are registered trademarks of Microsoft Corporation. Microwire is a trademark of National Semiconductor Corp. National Semiconductor is a registered trademark of National Semiconductor Corp. Texas Instruments is a registered trademark of Texas Instruments, Inc. Motorola and SPI are registered trademarks of Motorola, Inc. LINUX is a registered trademark of Linus Torvalds. 2010 Cirrus Logic All Rights Reserved DS638F2 |
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