EP7312-IV-90

EP7312-IV-90 Datasheet

EP7312 Data Sheet

Part	Datasheet
EP7312-IV-90	EP7312-IV-90 (pdf)

Related Parts	Information
EP7312M-CBZ	EP7312M-CBZ
EP7312-IB	EP7312-IB
EP7312-CV-90	EP7312-CV-90
EP7312-CV	EP7312-CV
EP7312-CR-90	EP7312-CR-90
EP7312-CVZ	EP7312-CVZ
EP7312-CVZ-90	EP7312-CVZ-90
EP7312-IBZ	EP7312-IBZ
EP7312-IR-90	EP7312-IR-90
EP7312-CR	EP7312-CR
EP7312-CBZ	EP7312-CBZ
EP7312-IVZ	EP7312-IVZ
EP7312-CB	EP7312-CB
EP7312-IV	EP7312-IV

PDF Datasheet Preview
EP7312 Data Sheet I Processor ARM7TDMI CPU operating at speeds of 74 and 90 MHz 8 KBytes of four-way set-associative cache MMU with 64-entry TLB Thumb code support enabled I Ultra low power 90 mW at 74 MHz typical 108 mW at 90 MHz typical mW in the Standby State I Advanced audio decoder/decompression capability Supports bit streams with adaptive bit rates Allows for support of multiple audio decompression algorithms MP3, WMA, AAC, Audible, etc. BLOCK DIAGRAM cont. High-Performance, Low-Power System on Chip with SDRAM and Enhanced Digital Audio Interface OVERVIEW The Cirrus Logic EP7312 is designed for ultra-lowpower portable and line-powered applications such as portable consumer entertainment devices, home and car audio juke box systems, and general purpose industrial control applications, or any device that features the added capability of digital audio compression & decompression. The core-logic functionality of the device is built around an ARM720T processor with 8 KBytes of four-way set-associative unified cache and a write buffer. Incorporated into the ARM720T is an enhanced memory management unit MMU which allows for support of sophisticated operating systems like CE and ORDERING INFORMATION: See list of available parts with legend on page cont. SERIAL PORTS USER INTERFACE Digital Audio Interface Serial Interface Power Management 2 UARTs w/ IrDA Boot ROM Internal Data Bus EPB Bus ARM720T ICE-JTAG ARM7TDMI CPU Core 8 KB Cache Write Buffer Bus Bridge MaverickKeyTM Memory Controller SRAM I/F SDRAM I/F On-chip SRAM 48 KB Clocks & Timers Interrupts, PWM & GPIO Keypad& Touch Screen I/F LCD Controller MEMORY and STORAGE 2001, 2002 Cirrus Logic All Rights Reserved P.O. Box 17847, Austin, Texas 78760 512 445 7222 FAX 512 445 7581 MAY ’02 DS508PP5 EP7312 High-Performance, Low-Power System on Chip FEATURES cont I 48 KBytes of on-chip SRAM I MaverickKey IDs 32-bit unique ID can be used for DRM compliance 128-bit random ID I Available in 74 and 90 MHz clock speeds I LCD controller Interfaces directly to a single-scan panel monochrome STN LCD Interfaces to a single-scan panel color STN LCD with minimal external glue logic I Full JTAG boundary scan and Embedded support I Integrated Peripheral Interfaces 32-bit SDRAM Interface up to 2 external banks 8/32/16-bit SRAM/FLASH/ROM Interface Digital Audio Interface providing glueless interface to low-power DACs, ADCs and CODECs Two Synchronous Serial Interfaces SSI1, SSI2 CODEC Sound Interface 8x8 Keypad Scanner 208-Pin LQFP Package Characteristics 30 208-Pin LQFP Pin Diagram 31 208-Pin LQFP Numeric Pin Listing 32 204-Ball TFBGA Package Characteristics 38 204-Ball TFBGA Pinout Top View 39 204-Ball TFBGA Ball Listing 40 256-Ball PBGA Package Characteristics 47 256-Ball PBGA Pinout Top View 49 256-Ball PBGA Ball Listing 50 JTAG Boundary Scan Signal Ordering 55 CONVENTIONS 61 Acronyms and Abbreviations 61 Units of Measurement 61 General Conventions 62 Pin Description Conventions 62 Ordering Information 63 Ordering Information Legend 63 2001, 2002 Cirrus Logic All Rights Reserved DS508PP5 List of Figures EP7312 High-Performance, Low-Power System on Chip Figure A Fully-Configured EP7312-Based System Figure Legend for Timing Diagrams Figure SDRAM Load Mode Register Cycle Timing Measurement Figure SDRAM Burst Read Cycle Timing Measurement Figure SDRAM Burst Write Cycle Timing Measurement Figure SDRAM Refresh Cycle Timing Measurement Figure Static Memory Single Read Cycle Timing Measurement Figure Static Memory Single Write Cycle Timing Measurement Figure Static Memory Burst Read Cycle Timing Measurement Figure Static Memory Burst Write Cycle Timing Measurement Figure SSI1 Interface Timing Measurement Figure SSI2 Interface Timing Measurement Figure LCD Controller Timing Measurement Figure JTAG Timing Measurement Figure 208-Pin LQFP Package Outline Drawing Figure 208-Pin LQFP Low Profile Quad Flat Pack Pin Diagram Figure 204-Ball TFBGA Package Figure 256-Ball PBGA Package List of Tables Table Power Management Pin Assignments Table Static Memory Interface Pin Assignments Table SDRAM Interface Pin Assignments Table Universal Asynchronous Receiver/Transmitters Pin Assignments Table DAI Interface Pin Assignments Table CODEC Interface Pin Assignments Table SSI2 Interface Pin Assignments Table Serial Interface Pin Assignments Table LCD Interface Pin Assignments Table Keypad Interface Pin Assignments Table Interrupt Controller Pin Assignments Table Real-Time Clock Pin Assignments Table PLL and Clocking Pin Assignments Table DC-to-DC Converter Interface Pin Assignments Table General Purpose Input/Output Pin Assignments Table Hardware Debug Interface Pin Assignments Table LED Flasher Pin Assignments Table DAI/SSI2/CODEC Pin Multiplexing Table Pin Multiplexing Table 208-Pin LQFP Numeric Pin Listing Table 204-Ball TFBGA Ball Listing Table 256-Ball PBGA Ball Listing Table JTAG Boundary Scan Signal Ordering Table Acronyms and Abbreviations Table Unit of Measurement Table Pin Description Conventions DS508PP5 2001, 2002 Cirrus Logic All Rights Reserved EP7312 High-Performance, Low-Power System on Chip Description of the EP7312’s Components, Functionality, and Interfaces The following sections describe the EP7312 in more detail. Processor Core - ARM720T The EP7312 incorporates an ARM 32-bit RISC micro controller that controls a wide range of on-chip peripherals. The processor utilizes a three-stage pipeline consisting of fetch, decode and execute stages. Key features include: • ARM 32-bit and Thumb 16-bit compressed instruction sets • Enhanced MMU for Microsoft Windows CE and other operating systems • 8 KB of 4-way set-associative cache. • Translation Look Aside Buffers with 64 Translated Entries Power Management The EP7312 is designed for ultra-low-power operation. Its core operates at only V, while its I/O has an operation range of V. The device has three basic power states: • Operating This state is the full performance state. All the clocks and peripheral logic are enabled. • Idle This state is the same as the Operating State, except the CPU clock is halted while waiting for an event such as a key press. • Standby This state is equivalent to the computer being switched off no display , and the main oscillator shut down. An event such as a key press can wake-up the processor. Table 1 shows the power management pin assignments. Table Power Management Pin Assignments Pin Mnemonic Pin Description BATOK nEXTPWR nPWRFL nBATCHG Battery ok input External power supply sense input Power fail sense input Battery changed sense input MaverickKey Unique ID MaverickKey unique hardware programmed IDs are a solution to the growing concern over secure web content and commerce. With Internet security playing an important role in the delivery of digital media such as books or music, traditional software methods are quickly becoming unreliable. The MaverickKey unique IDs provide OEMs with a method of utilizing specific hardware IDs such as those assigned for SDMI Secure Digital Music Initiative or any other authentication mechanism. Both a specific 32-bit ID as well as a 128-bit random ID is programmed into the EP7312 through the use of laser probing technology. These IDs can then be used to match secure copyrighted content with the ID of the target device the EP7312 is powering, and then deliver the copyrighted information over a secure connection. In addition, secure transactions can benefit by also matching device IDs to server IDs. MaverickKey IDs provide a level of hardware security required for today’s Internet appliances. Memory Interfaces There are two main external memory interfaces. The first one is the ROM/SRAM/FLASH-style interface that has programmable wait-state timings and includes burstmode capability, with six chip selects decoding six 256 MB sections of addressable space. For maximum flexibility, each bank can be specified to be 8-, 16-, or 32bits wide. This allows the use of 8-bit-wide boot ROM options to minimize overall system cost. The on-chip boot ROM can be used in product manufacturing to serially download system code into system FLASH memory. To further minimize system memory requirements and cost, the ARM Thumb instruction set is supported, providing for the use of high-speed 32-bit operations in 16-bit op-codes and yielding industryleading code density. shows the Static Memory Interface pin assignments. Table Static Memory Interface Pin Assignments Pin Mnemonic Pin Description nCS[5:0] A[27:0] D[31:0] nMOE/nSDCAS nMWE/nSDWE HALFWORD WORD WRITE/nSDRAS Note Note O Chip select out JTAG Boundary Scan Signal Ordering Table JTAG Boundary Scan Signal Ordering LQFP TFBGA PBGA Pin No. Ball Ball Signal Type nCS[5] EXPCLK WORD WRITE/nSDRAS Position 1 3 6 8 DS508PP5 2001, 2002 Cirrus Logic All Rights Reserved EP7312 High-Performance, Low-Power System on Chip Table JTAG Boundary Scan Signal Ordering Continued LQFP TFBGA PBGA Pin No. Ball Ball Signal Type Position RUN/CLKEN EXPRDY TXD2 RXD2 PB[7] PB[6] PB[5] PB[4] PB[3] PB[2] PB[1] PB[0] PA[7] PA[6] PA[5] PA[4] PA[3] PA[2] PA[1] PA[0] LEDDRV TXD1 PHDIN CTS RXD1 DCD DSR nTEST1 nTEST0 EINT3 nEINT2 nEINT1 nEXTFIQ PE[2]/CLKSEL PE[1]/ BOOTSEL[1] PE[0]/BOOTSEL0 PD[7]/SDQM[1] PD[6/SDQM[0]] 2001, 2002 Cirrus Logic All Rights Reserved DS508PP5 DS508PP5 EP7312 High-Performance, Low-Power System on Chip Table JTAG Boundary Scan Signal Ordering Continued LQFP TFBGA PBGA Pin No. Ball Ball Signal Type Position V209 PD[5] PD[4] PD[3] PD[2] PD[1] PD[0]/LEDFLSH SSIRXFR ADCIN nADCCS DRIVE1 DRIVE0 ADCCLK ADCOUT SMPCLK FB1 FB0 COL7 COL6 COL5 COL4 COL3 COL2 COL1 COL0 BUZ D[31] D[30] D[29] D[28] A[27]/DRA[0] D[27] A[26]/DRA[1] D[26] A[25]/DRA[2] D[25] HALFWORD A[24]/DRA[3] D[24] 2001, 2002 Cirrus Logic All Rights Reserved EP7312 High-Performance, Low-Power System on Chip Table JTAG Boundary Scan Signal Ordering Continued LQFP TFBGA PBGA Pin No. Ball Ball Signal Type Position A[23]/DRA[4] D[23] A[22]/DRA[5] D[22] A[21]/DRA[6] D[21] A[20]/DRA[7] D[20] A[19]/DRA[8] D[19] A[18]/DRA[9] D[18] A[17]/DRA[10] D[17] A[16]/DRA[11] D[16] A[15]/DRA[12] D[15] A[14]/DRA[13] D[14] A[13]/DRA[14] D[13] A[12] D[12] A[11] D[11] A[10] D[10] A[9] D[9] A[8] D[8] A[7] D[7] nBATCHG nEXTPWR BATOK nPOR 2001, 2002 Cirrus Logic All Rights Reserved DS508PP5 EP7312 High-Performance, Low-Power System on Chip Table JTAG Boundary Scan Signal Ordering Continued LQFP TFBGA PBGA Pin No. Ball Ball Signal Type Position nMEDCHG/nBROM nURESET WAKEUP nPWRFL A[6] D[6] A[5] D[5] A[4] D[4] A[3] D[3] A[2] D[2] A[1] D[1] A[0] D[0] CL2 CL1 FRM M DD[3] DD[2] DD[1] DD[0] nSDCS[1] nSDCS[0] SDQM[3] SDQM[2] SDCKE SDCLK nMWE/nSDWE nMOE/nSDCAS nCS[0] nCS[1] DS508PP5 2001, 2002 Cirrus Logic All Rights Reserved EP7312 High-Performance, Low-Power System on Chip Table JTAG Boundary Scan Signal Ordering Continued LQFP TFBGA PBGA Pin No. Ball Ball Signal Type Position nCS[2] nCS[3] nCS[4] 1 See EP7312 Users’ Manual for pin naming / functionality. 2 For each pad, the JTAG connection ordering is input, output, then enable as applicable. 2001, 2002 Cirrus Logic All Rights Reserved DS508PP5 EP7312 High-Performance, Low-Power System on Chip CONVENTIONS This section presents acronyms, abbreviations, units of measurement, and conventions used in this data sheet. Acronyms and Abbreviations Table 24 lists abbreviations and acronyms used in this data sheet. Table Acronyms and Abbreviations Acronym/ Abbreviation Definition A/D ADC CODEC D/A DMA EPB FCS FIFO FIQ GPIO ICT IR IRQ IrDA JTAG LCD LED LQFP LSB MIPS MMU MSB PBGA PCB PDA PLL p/u RISC RTC SIR SRAM SSI analog-to-digital analog-to-digital converter coder / decoder digital-to-analog direct-memory access embedded peripheral bus frame check sequence first in / first out fast interrupt request general purpose I/O in circuit test infrared standard interrupt request Infrared Data Association Joint Test Action Group liquid crystal display light-emitting diode low profile quad flat pack least significant bit millions of instructions per second memory management unit most significant bit plastic ball grid array printed circuit board personal digital assistant phase locked loop pull-up resistor reduced instruction set computer Real-Time Clock slow kbps infrared static random access memory synchronous serial interface Table Acronyms and Abbreviations Continued Acronym/ Abbreviation Definition TAP TLB UART test access port translation lookaside buffer universal asynchronous receiver Units of Measurement Table Unit of Measurement Unit of Measure degree Celsius fs Hz kbps KB kHz Mbps MB MBps MHz µA µF µW µs mA mW ms ns V W sample frequency hertz cycle per second kilobits per second kilobyte 1,024 bytes kilohertz kilo Ohm megabits 1,048,576 bits per second megabyte 1,048,576 bytes megabytes per second megahertz 1,000 kilohertz microampere microfarad microwatt microsecond 1,000 nanoseconds milliampere milliwatt millisecond 1,000 microseconds nanosecond volt watt DS508PP5 2001, 2002 Cirrus Logic All Rights Reserved EP7312 High-Performance, Low-Power System on Chip General Conventions Hexadecimal numbers are presented with all letters in uppercase and a lowercase “h” appended or with a 0x at the beginning. For example, 0x14 and 03CAh are hexadecimal numbers. Binary numbers are enclosed in single quotation marks when in text for example, ‘11’ designates a binary number . Numbers not indicated by an “h”, 0x or quotation marks are decimal. Registers are referred to by acronym, with bits listed in brackets separated by a colon for example, CODR[7:0] , and are described in the EP7312 User’s Manual. The use of “TBD” indicates values that are “to be determined,” “n/a” designates “not available,” and “n/c” indicates a pin that is a “no connect.” Pin Description Conventions Abbreviations used for signal directions are listed in Table Table Pin Description Conventions Abbreviation Direction Input Output Input or Output 2001, 2002 Cirrus Logic All Rights Reserved DS508PP5 EP7312 High-Performance, Low-Power System on Chip Ordering Information Here is the list of EP7312 parts that are available: EP7312-CV EP7312-CB EP7312-CV-90 EP7312-CR-90 EP7312-IR EP7312-IB-90 EP7312-IV EP7312-CR EP7312-CB-90 EP7312-IB EP7312-IV-90 EP7312-IR-90 Ordering Information Legend Here is the legend for understanding the ordering information on page EP7312 CV Product Line Embedded Processor Processor Speed Package Type V = Low Profile Quad Flat Pack 208-pin LQFP B = Plastic Ball Grid Array 17 mm x 17 mm 256-ball PBGA R = Reduced Ball Grid Array 13 mm x 13 mm 204-pin TFBGA Temperature Range C = Commercial E = Extended Operating Version I = Industrial Operating Version Note Go to the Cirrus Logic Internet site at to find contact information for your local sales representative. DS508PP5 2001, 2002 Cirrus Logic All Rights Reserved

PDF Datasheet Preview

EP7312 Data Sheet

I Processor ARM7TDMI CPU operating at speeds of 74 and 90 MHz 8 KBytes of four-way set-associative cache MMU with 64-entry TLB Thumb code support enabled

I Ultra low power 90 mW at 74 MHz typical 108 mW at 90 MHz typical mW in the Standby State

I Advanced audio decoder/decompression capability Supports bit streams with adaptive bit rates Allows for support of multiple audio decompression algorithms MP3, WMA, AAC, Audible, etc.

BLOCK DIAGRAM
cont.

High-Performance, Low-Power System on Chip with

SDRAM and Enhanced Digital Audio Interface

OVERVIEW

The Cirrus Logic EP7312 is designed for ultra-lowpower portable and line-powered applications such as portable consumer entertainment devices, home and car audio juke box systems, and general purpose industrial control applications, or any device that features the added capability of digital audio compression & decompression. The core-logic functionality of the device is built around an ARM720T processor with 8 KBytes of four-way set-associative unified cache and a write buffer. Incorporated into the ARM720T is an enhanced memory management unit MMU which allows for support of sophisticated operating systems like CE and
ORDERING INFORMATION:

See list of available parts with legend on page
cont.

SERIAL PORTS

USER INTERFACE

Digital Audio Interface

Serial Interface

Power Management
2 UARTs w/ IrDA

Boot ROM

Internal Data Bus

EPB Bus

ARM720T

ICE-JTAG

ARM7TDMI CPU Core
8 KB Cache

Write Buffer

Bus Bridge

MaverickKeyTM

Memory Controller

SRAM I/F

SDRAM I/F

On-chip SRAM 48 KB

Clocks & Timers

Interrupts, PWM & GPIO

Keypad& Touch

Screen I/F

LCD Controller

MEMORY and STORAGE
2001, 2002 Cirrus Logic All Rights Reserved

P.O. Box 17847, Austin, Texas 78760 512 445 7222 FAX 512 445 7581

MAY ’02 DS508PP5

EP7312 High-Performance, Low-Power System on Chip

FEATURES cont

I 48 KBytes of on-chip SRAM I MaverickKey IDs
32-bit unique ID can be used for DRM compliance 128-bit random ID

I Available in 74 and 90 MHz clock speeds I LCD controller

Interfaces directly to a single-scan panel monochrome STN LCD

Interfaces to a single-scan panel color STN LCD with minimal external glue logic

I Full JTAG boundary scan and Embedded support

I Integrated Peripheral Interfaces 32-bit SDRAM Interface up to 2 external banks 8/32/16-bit SRAM/FLASH/ROM Interface Digital Audio Interface providing glueless interface to low-power DACs, ADCs and CODECs Two Synchronous Serial Interfaces SSI1, SSI2 CODEC Sound Interface 8x8 Keypad Scanner
208-Pin LQFP Package Characteristics 30 208-Pin LQFP Pin Diagram 31 208-Pin LQFP Numeric Pin Listing 32 204-Ball TFBGA Package Characteristics 38 204-Ball TFBGA Pinout Top View 39 204-Ball TFBGA Ball Listing 40 256-Ball PBGA Package Characteristics 47 256-Ball PBGA Pinout Top View 49 256-Ball PBGA Ball Listing 50 JTAG Boundary Scan Signal Ordering 55

CONVENTIONS 61

Acronyms and Abbreviations 61 Units of Measurement 61 General Conventions 62 Pin Description Conventions 62
Ordering Information 63
Ordering Information Legend 63
2001, 2002 Cirrus Logic All Rights Reserved

DS508PP5

List of Figures

EP7312 High-Performance, Low-Power System on Chip

Figure A Fully-Configured EP7312-Based System Figure Legend for Timing Diagrams Figure SDRAM Load Mode Register Cycle Timing Measurement Figure SDRAM Burst Read Cycle Timing Measurement Figure SDRAM Burst Write Cycle Timing Measurement Figure SDRAM Refresh Cycle Timing Measurement Figure Static Memory Single Read Cycle Timing Measurement Figure Static Memory Single Write Cycle Timing Measurement Figure Static Memory Burst Read Cycle Timing Measurement Figure Static Memory Burst Write Cycle Timing Measurement Figure SSI1 Interface Timing Measurement Figure SSI2 Interface Timing Measurement Figure LCD Controller Timing Measurement Figure JTAG Timing Measurement Figure 208-Pin LQFP Package Outline Drawing Figure 208-Pin LQFP Low Profile Quad Flat Pack Pin Diagram Figure 204-Ball TFBGA Package Figure 256-Ball PBGA Package

List of Tables
Table Power Management Pin Assignments Table Static Memory Interface Pin Assignments Table SDRAM Interface Pin Assignments Table Universal Asynchronous Receiver/Transmitters Pin Assignments Table DAI Interface Pin Assignments Table CODEC Interface Pin Assignments Table SSI2 Interface Pin Assignments Table Serial Interface Pin Assignments Table LCD Interface Pin Assignments Table Keypad Interface Pin Assignments Table Interrupt Controller Pin Assignments Table Real-Time Clock Pin Assignments Table PLL and Clocking Pin Assignments Table DC-to-DC Converter Interface Pin Assignments Table General Purpose Input/Output Pin Assignments Table Hardware Debug Interface Pin Assignments Table LED Flasher Pin Assignments Table DAI/SSI2/CODEC Pin Multiplexing Table Pin Multiplexing Table 208-Pin LQFP Numeric Pin Listing Table 204-Ball TFBGA Ball Listing Table 256-Ball PBGA Ball Listing Table JTAG Boundary Scan Signal Ordering Table Acronyms and Abbreviations Table Unit of Measurement Table Pin Description Conventions

DS508PP5
2001, 2002 Cirrus Logic All Rights Reserved

EP7312 High-Performance, Low-Power System on Chip

Description of the EP7312’s Components, Functionality, and Interfaces

The following sections describe the EP7312 in more detail.

Processor Core - ARM720T

The EP7312 incorporates an ARM 32-bit RISC micro controller that controls a wide range of on-chip peripherals. The processor utilizes a three-stage pipeline consisting of fetch, decode and execute stages. Key features include:
• ARM 32-bit and Thumb 16-bit compressed instruction sets
• Enhanced MMU for Microsoft Windows CE and other operating systems
• 8 KB of 4-way set-associative cache.
• Translation Look Aside Buffers with 64 Translated

Entries

Power Management

The EP7312 is designed for ultra-low-power operation. Its core operates at only V, while its I/O has an operation range of V. The device has three basic power states:
• Operating This state is the full performance state. All the clocks and peripheral logic are enabled.
• Idle This state is the same as the Operating State, except the CPU clock is halted while waiting for an event such as a key press.
• Standby This state is equivalent to the computer being switched off no display , and the main oscillator shut down. An event such as a key press can wake-up the processor.

Table 1 shows the power management pin assignments.

Table Power Management Pin Assignments

Pin Mnemonic

Pin Description

BATOK nEXTPWR nPWRFL nBATCHG

Battery ok input

External power supply sense input

Power fail sense input

Battery changed sense input

MaverickKey Unique ID

MaverickKey unique hardware programmed IDs are a solution to the growing concern over secure web content and commerce. With Internet security playing an important role in the delivery of digital media such as books or music, traditional software methods are quickly
becoming unreliable. The MaverickKey unique IDs provide OEMs with a method of utilizing specific hardware IDs such as those assigned for SDMI Secure Digital Music Initiative or any other authentication mechanism.

Both a specific 32-bit ID as well as a 128-bit random ID is programmed into the EP7312 through the use of laser probing technology. These IDs can then be used to match secure copyrighted content with the ID of the target device the EP7312 is powering, and then deliver the copyrighted information over a secure connection. In addition, secure transactions can benefit by also matching device IDs to server IDs. MaverickKey IDs provide a level of hardware security required for today’s Internet appliances.

Memory Interfaces

There are two main external memory interfaces. The first one is the ROM/SRAM/FLASH-style interface that has programmable wait-state timings and includes burstmode capability, with six chip selects decoding six 256 MB sections of addressable space. For maximum flexibility, each bank can be specified to be 8-, 16-, or 32bits wide. This allows the use of 8-bit-wide boot ROM options to minimize overall system cost. The on-chip boot ROM can be used in product manufacturing to serially download system code into system FLASH memory. To further minimize system memory requirements and cost, the ARM Thumb instruction set is supported, providing for the use of high-speed 32-bit operations in 16-bit op-codes and yielding industryleading code density. shows the Static Memory Interface pin assignments.

Table Static Memory Interface Pin Assignments

Pin Mnemonic

Pin Description
nCS[5:0] A[27:0] D[31:0] nMOE/nSDCAS nMWE/nSDWE

HALFWORD

WORD WRITE/nSDRAS

Note

Note

O Chip select out
JTAG Boundary Scan Signal Ordering
Table JTAG Boundary Scan Signal Ordering

LQFP TFBGA PBGA

Pin No. Ball

Ball

Signal

Type
nCS[5]

EXPCLK

WORD

WRITE/nSDRAS

Position
1 3 6 8

DS508PP5
2001, 2002 Cirrus Logic All Rights Reserved

EP7312 High-Performance, Low-Power System on Chip
Table JTAG Boundary Scan Signal Ordering Continued

LQFP TFBGA PBGA

Pin No. Ball

Ball

Signal

Type Position

RUN/CLKEN EXPRDY TXD2 RXD2 PB[7] PB[6] PB[5] PB[4] PB[3] PB[2] PB[1] PB[0] PA[7] PA[6] PA[5] PA[4] PA[3] PA[2] PA[1] PA[0] LEDDRV TXD1 PHDIN CTS RXD1 DCD DSR nTEST1 nTEST0 EINT3 nEINT2 nEINT1 nEXTFIQ

PE[2]/CLKSEL PE[1]/

BOOTSEL[1] PE[0]/BOOTSEL0

PD[7]/SDQM[1] PD[6/SDQM[0]]
2001, 2002 Cirrus Logic All Rights Reserved

DS508PP5

DS508PP5

EP7312 High-Performance, Low-Power System on Chip
Table JTAG Boundary Scan Signal Ordering Continued

LQFP TFBGA PBGA

Pin No. Ball

Ball

Signal

Type Position

V209

PD[5] PD[4] PD[3] PD[2] PD[1] PD[0]/LEDFLSH SSIRXFR ADCIN nADCCS DRIVE1 DRIVE0 ADCCLK ADCOUT SMPCLK FB1 FB0 COL7 COL6 COL5 COL4 COL3 COL2 COL1 COL0 BUZ D[31] D[30] D[29] D[28] A[27]/DRA[0] D[27] A[26]/DRA[1] D[26] A[25]/DRA[2] D[25] HALFWORD A[24]/DRA[3] D[24]
2001, 2002 Cirrus Logic All Rights Reserved

EP7312 High-Performance, Low-Power System on Chip
Table JTAG Boundary Scan Signal Ordering Continued

LQFP TFBGA PBGA

Pin No. Ball

Ball

Signal

Type Position

A[23]/DRA[4] D[23]

A[22]/DRA[5] D[22]

A[21]/DRA[6] D[21]

A[20]/DRA[7] D[20]

A[19]/DRA[8] D[19]

A[18]/DRA[9] D[18]

A[17]/DRA[10] D[17]

A[16]/DRA[11] D[16]

A[15]/DRA[12] D[15]

A[14]/DRA[13] D[14]

A[13]/DRA[14] D[13] A[12] D[12] A[11] D[11] A[10] D[10] A[9] D[9] A[8] D[8] A[7] D[7]
nBATCHG nEXTPWR

BATOK nPOR
2001, 2002 Cirrus Logic All Rights Reserved

DS508PP5

EP7312 High-Performance, Low-Power System on Chip
Table JTAG Boundary Scan Signal Ordering Continued

LQFP TFBGA PBGA

Pin No. Ball

Ball

Signal

Type Position
nMEDCHG/nBROM nURESET WAKEUP nPWRFL A[6] D[6] A[5] D[5] A[4] D[4] A[3] D[3] A[2] D[2] A[1] D[1] A[0] D[0] CL2 CL1 FRM M DD[3] DD[2] DD[1] DD[0] nSDCS[1] nSDCS[0] SDQM[3] SDQM[2] SDCKE SDCLK
nMWE/nSDWE nMOE/nSDCAS
nCS[0] nCS[1]

DS508PP5
2001, 2002 Cirrus Logic All Rights Reserved

EP7312 High-Performance, Low-Power System on Chip
Table JTAG Boundary Scan Signal Ordering Continued

LQFP TFBGA PBGA

Pin No. Ball

Ball

Signal

Type Position
nCS[2] nCS[3] nCS[4]
1 See EP7312 Users’ Manual for pin naming / functionality. 2 For each pad, the JTAG connection ordering is input, output, then enable as applicable.
2001, 2002 Cirrus Logic All Rights Reserved

DS508PP5

EP7312 High-Performance, Low-Power System on Chip

CONVENTIONS

This section presents acronyms, abbreviations, units of measurement, and conventions used in this data sheet.

Acronyms and Abbreviations

Table 24 lists abbreviations and acronyms used in this data sheet.

Table Acronyms and Abbreviations

Acronym/ Abbreviation

Definition

A/D ADC CODEC D/A DMA EPB FCS FIFO FIQ GPIO ICT IR IRQ IrDA JTAG LCD LED LQFP LSB MIPS MMU MSB PBGA PCB PDA PLL p/u RISC RTC SIR SRAM SSI
analog-to-digital analog-to-digital converter coder / decoder digital-to-analog direct-memory access embedded peripheral bus frame check sequence first in / first out fast interrupt request general purpose I/O in circuit test infrared standard interrupt request Infrared Data Association Joint Test Action Group liquid crystal display light-emitting diode low profile quad flat pack least significant bit millions of instructions per second memory management unit most significant bit plastic ball grid array printed circuit board personal digital assistant phase locked loop pull-up resistor reduced instruction set computer Real-Time Clock slow kbps infrared static random access memory synchronous serial interface

Table Acronyms and Abbreviations Continued

Acronym/ Abbreviation

Definition

TAP TLB UART
test access port translation lookaside buffer universal asynchronous receiver

Units of Measurement

Table Unit of Measurement

Unit of Measure
degree Celsius
fs Hz kbps KB kHz Mbps MB MBps MHz µA µF µW µs mA mW ms ns V W
sample frequency hertz cycle per second kilobits per second kilobyte 1,024 bytes kilohertz kilo Ohm megabits 1,048,576 bits per second megabyte 1,048,576 bytes megabytes per second megahertz 1,000 kilohertz microampere microfarad microwatt microsecond 1,000 nanoseconds milliampere milliwatt millisecond 1,000 microseconds nanosecond volt watt

DS508PP5
2001, 2002 Cirrus Logic All Rights Reserved

EP7312 High-Performance, Low-Power System on Chip

General Conventions

Hexadecimal numbers are presented with all letters in uppercase and a lowercase “h” appended or with a 0x at the beginning. For example, 0x14 and 03CAh are hexadecimal numbers. Binary numbers are enclosed in single quotation marks when in text for example, ‘11’ designates a binary number . Numbers not indicated by an “h”, 0x or quotation marks are decimal.

Registers are referred to by acronym, with bits listed in brackets separated by a colon for example, CODR[7:0] , and are described in the EP7312 User’s Manual. The use of “TBD” indicates values that are “to be determined,” “n/a” designates “not available,” and “n/c” indicates a pin that is a “no connect.”

Pin Description Conventions

Abbreviations used for signal directions are listed in Table

Table Pin Description Conventions

Abbreviation

Direction

Input

Output

Input or Output
2001, 2002 Cirrus Logic All Rights Reserved

DS508PP5

EP7312 High-Performance, Low-Power System on Chip
Ordering Information

Here is the list of EP7312 parts that are available:

EP7312-CV EP7312-CB EP7312-CV-90 EP7312-CR-90 EP7312-IR EP7312-IB-90

EP7312-IV EP7312-CR EP7312-CB-90 EP7312-IB EP7312-IV-90 EP7312-IR-90
Ordering Information Legend
Here is the legend for understanding the ordering information on page

EP7312 CV

Product Line Embedded Processor

Processor Speed

Package Type V = Low Profile Quad Flat Pack 208-pin LQFP B = Plastic Ball Grid Array 17 mm x 17 mm 256-ball PBGA R = Reduced Ball Grid Array 13 mm x 13 mm 204-pin TFBGA

Temperature Range C = Commercial E = Extended Operating Version I = Industrial Operating Version

Note Go to the Cirrus Logic Internet site at to find contact information for your local sales representative.

DS508PP5
2001, 2002 Cirrus Logic All Rights Reserved

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived EP7312-IV-90 Datasheet file may be downloaded here without warranties.

Datasheet ID: EP7312-IV-90 523228