EP7311-IV-90

EP7311-IV-90 Datasheet

EP7311 Data Sheet

Part	Datasheet
EP7311-IV-90	EP7311-IV-90 (pdf)

Related Parts	Information
EP7311-IB	EP7311-IB
EP7311-CB	EP7311-CB
EP7311-CB-90	EP7311-CB-90
EP7311-CV-90	EP7311-CV-90
EP7311-IR	EP7311-IR
EP7311-IR-90	EP7311-IR-90
EP7311-IV	EP7311-IV
EP7311-CV	EP7311-CV
EP7311M-IBZ	EP7311M-IBZ

PDF Datasheet Preview
• ARM720T Processor ARM7TDMI CPU 8 KB of four-way set-associative cache MMU with 64-entry TLB Thumb code support enabled • Ultra low power 90 mW at 74 MHz typical 30 mW at 18 MHz typical 10 mW in the Idle State <1 mW in the Standby State • 48 KB of on-chip SRAM • MaverickKey IDs 32-bit unique ID can be used for SDMI compliance 128-bit random ID • Dynamically programmable clock speeds of 18, 36, 49, and 74 MHz EP7311 Data Sheet High-performance, Low-power, System-on-chip with SDRAM & Enhanced Digital Audio Interface OVERVIEW The Maverick EP7311 is designed for ultra-low-power applications such as PDAs, smart cellular phones, and industrial hand held information appliances. The core-logic functionality of the device is built around an ARM720T processor with 8 KB of four-way set-associative unified cache and a write buffer. Incorporated into the ARM720T is an enhanced memory management unit MMU which allows for support of sophisticated operating systems like BLOCK DIAGRAM cont. cont. SERIAL PORTS USER INTERFACE Multimedia Codec Port Serial Interface Power Management 2 UARTs w/ IrDA Boot ROM Internal Data Bus EPB Bus ARM720T ICE-JTAG ARM7TDMI CPU Core 8 KB Write Cache Buffer Bus Bridge MaverickKeyTM Memory Controller SRAM I/F SDRAM I/F On-chip SRAM 48 KB Clocks & Timers Interrupts, PWM & GPIO Keypad& Touch Screen I/F LCD Controller MEMORY AND STORAGE Copyright Cirrus Logic, Inc. 2005 All Rights Reserved AUG ‘05 DS506F1 EP7311 High-Performance, Low-Power System on Chip FEATURES cont 256-Ball PBGA Package Specifications 38 256-Ball PBGA Pinout Top View 39 256-Ball PBGA Ball Listing 39 JTAG Boundary Scan Signal Ordering 43 CONVENTIONS 48 Acronyms and Abbreviations 48 Units of Measurement 48 General Conventions 49 Pin Description Conventions 49 Ordering Information 50 Environmental, Manufacturing, & Handling Information 50 Copyright Cirrus Logic, Inc. 2005 All Rights Reserved DS506F1 List of Figures EP7311 High-Performance, Low-Power System on Chip Figure A Maximum EP7309 Based System Figure Legend for Timing Diagrams Figure Static Memory Single Read Cycle Timing Measurement Figure Static Memory Single Write Cycle Timing Measurement Figure Static Memory Burst Read Cycle Timing Measurement Figure Static Memory Burst Write Cycle Timing Measurement Figure SSI1 Interface Timing Measurement Figure SSI2 Interface Timing Measurement Figure LCD Controller Timing Measurement Figure JTAG Timing Measurement Figure 208-Pin LQFP Package Outline Drawing Figure 208-Pin LQFP Low Profile Quad Flat Pack Pin Diagram Figure 204-Ball TFBGA Package Figure 256-Ball PBGA Package List of Tables Table Power Management Pin Assignments Table Static Memory Interface Pin Assignments Table Universal Asynchronous Receiver/Transmitters Pin Assignments Table DAI Interface Pin Assignments Table CODEC Interface Pin Assignments Table SSI2 Interface Pin Assignments Table Serial Interface Pin Assignments Table LCD Interface Pin Assignments Table Keypad Interface Pin Assignments Table Interrupt Controller Pin Assignments Table Real-Time Clock Pin Assignments Table PLL and Clocking Pin Assignments Table DC-to-DC Converter Interface Pin Assignments Table General Purpose Input/Output Pin Assignments Table Hardware Debug Interface Pin Assignments Table LED Flasher Pin Assignments Table DAI/SSI2/CODEC Pin Multiplexing Table Pin Multiplexing Table 208-Pin LQFP Numeric Pin Listing Table 204-Ball TFBGA Ball Listing Table 256-Ball PBGA Ball Listing Table JTAG Boundary Scan Signal Ordering Table Acronyms and Abbreviations Table Unit of Measurement Table Pin Description Conventions DS506F1 Copyright Cirrus Logic, Inc. 2005 All Rights Reserved EP7311 High-Performance, Low-Power System on Chip Processor Core - ARM720T The EP7311 incorporates an ARM 32-bit RISC microcontroller that controls a wide range of on-chip peripherals. The processor utilizes a three-stage pipeline consisting of fetch, decode and execute stages. Key features include: • ARM 32-bit and Thumb 16-bit compressed instruction sets • Enhanced MMU for Microsoft Windows CE and other operating systems • 8 KB of 4-way set-associative cache. • Translation Look Aside Buffers with 64 Translated Entries Power Management The EP7311 is designed for ultra-low-power operation. Its core operates at only V, while its I/O has an operation range of V allowing the device to achieve a performance level equivalent to 60 MIPS. The device has three basic power states: • Operating This state is the full performance state. All the clocks and peripheral logic are enabled. • Idle This state is the same as the Operating State, except the CPU clock is halted while waiting for an event such as a key press. • Standby This state is equivalent to the computer being switched off no display , and the main oscillator shut down. An event such as a key press can wake-up the processor. Pin Mnemonic Pin Description BATOK nEXTPWR nPWRFL nBATCHG Battery ok input External power supply sense input Power fail sense input Battery changed sense input Table A. Power Management Pin Assignments MaverickKey Unique ID MaverickKey unique hardware programmed IDs are a solution to the growing concern over secure web content and commerce. With Internet security playing an important role in the delivery of digital media such as books or music, traditional software methods are quickly becoming unreliable. The MaverickKey unique IDs provide OEMs with a method of utilizing specific hardware IDs such as those assigned for SDMI Secure Digital Music Initiative or any other authentication mechanism. Both a specific 32-bit ID as well as a 128-bit random ID is programmed into the EP7311 through the use of laser probing technology. These IDs can then be used to match secure copyrighted content with the ID of the target device the EP7311 is powering, and then deliver the copyrighted information over a secure connection. In addition, secure transactions can benefit by also matching device IDs to server IDs. MaverickKey IDs provide a level of hardware security required for today’s Internet appliances. Memory Interfaces There are two main external memory interfaces. The first one is the ROM/SRAM/FLASH-style interface that has programmable wait-state timings and includes burst-mode capability, with six chip selects decoding six 256 MB sections of addressable space. For maximum flexibility, each bank can be specified to be 8-, 16-, or 32-bits wide. This allows the use of 8-bit-wide boot ROM options to minimize overall system cost. The on-chip boot ROM can be used in product manufacturing to serially download system code into system FLASH memory. To further minimize system memory requirements and cost, the ARM Thumb instruction set is supported, providing for the use of high-speed 32-bit operations in 16-bit op-codes and yielding industry-leading code density. Pin Mnemonic Pin Description nCS[5:0] A[27:0] D[31:0] nMOE/nSDCAS nMWE/nSDWE HALFWORD WORD WRITE/nSDRAS Note Note O Chip select out O Address output I/O Data I/O O ROM expansion OP enable O ROM expansion write enable Halfword access select output JTAG Boundary Scan Signal Ordering EP7311 High-Performance, Low-Power System on Chip Table W. JTAG Boundary Scan Signal Ordering LQFP TFBGA PBGA Pin No. Ball Ball Signal Type nCS[5] EXPCLK WORD WRITE/nSDRAS RUN/CLKEN EXPRDY TXD2 RXD2 PB[7] PB[6] PB[5] PB[4] PB[3] PB[2] PB[1]/PRDY2 PB[0]/PRDY1 PA[7] PA[6] PA[5] PA[4] PA[3] PA[2] PA[1] PA[0] LEDDRV TXD1 PHDIN RXD1 nTEST1 nTEST0 EINT3 nEINT2 nEINT1 Position 1 3 6 8 10 13 14 16 17 20 23 26 29 32 35 38 41 44 47 50 53 56 59 62 65 67 69 70 71 72 73 74 75 76 77 78 Table W. JTAG Boundary Scan Signal Ordering Continued LQFP TFBGA PBGA Pin No. Ball Ball Signal Type Position nEXTFIQ PE[2]/CLKSEL PE[1]/BOOTSEL1 PE[0]/BOOTSEL0 PD[7]/SDQM[1] PD[6/SDQM[0]] PD[5] PD[4] PD[3] PD[2] PD[1] PD[0]/LEDFLSH SSIRXFR ADCIN nADCCS DRIVE1 DRIVE0 ADCCLK ADCOUT SMPCLK FB1 FB0 COL7 COL6 COL5 COL4 COL3 COL2 COL1 COL0 BUZ D[31] D[30] D[29] D[28] A[27]/DRA[0] D[27] A[26]/DRA[1] Copyright Cirrus Logic, Inc. 2005 All Rights Reserved DS506F1 DS506F1 EP7311 High-Performance, Low-Power System on Chip Table W. JTAG Boundary Scan Signal Ordering Continued LQFP TFBGA PBGA Pin No. Ball Ball Signal Type Position D[26] A[25]/DRA[2] D[25] HALFWORD A[24]/DRA[3] D[24] A[23]/DRA[4] D[23] A[22]/DRA[5] D[22] A[21]/DRA[6] D[21] A[20]/DRA[7] D[20] A[19]/DRA[8] D[19] A[18]/DRA[9] D[18] A[17]/DRA[10] D[17] A[16]/DRA[11] D[16] A[15]/DRA[12] D[15] A[14]/DRA[13] D[14] A[13]/DRA[14] D[13] A[12] D[12] A[11] D[11] A[10] D[10] A[9] D[9] A[8] D[8] Copyright Cirrus Logic, Inc. 2005 All Rights Reserved EP7311 High-Performance, Low-Power System on Chip Table W. JTAG Boundary Scan Signal Ordering Continued LQFP TFBGA PBGA Pin No. Ball Ball Signal Type Position A[7] D[7] nBATCHG nEXTPWR BATOK nPOR nMEDCHG/nBROM nURESET WAKEUP nPWRFL A[6] D[6] A[5] D[5] A[4] D[4] A[3] D[3] A[2] D[2] A[1] D[1] A[0] D[0] CL2 CL1 FRM M DD[3] DD[2] DD[1] DD[0] nSDCS[1] nSDCS[0] SDQM[3] SDQM[2] SDCKE SDCLK Copyright Cirrus Logic, Inc. 2005 All Rights Reserved DS506F1 EP7311 High-Performance, Low-Power System on Chip Table W. JTAG Boundary Scan Signal Ordering Continued LQFP TFBGA PBGA Pin No. Ball Ball Signal Type Position nMWE/nSDWE nMOE/nSDCAS nCS[0] nCS[1] nCS[2] nCS[3] nCS[4] 1 See EP7311 Users’ Manual for pin naming / functionality. 2 For each pad, the JTAG connection ordering is input, output, then enable as applicable. DS506F1 Copyright Cirrus Logic, Inc. 2005 All Rights Reserved EP7311 High-Performance, Low-Power System on Chip CONVENTIONS This section presents acronyms, abbreviations, units of measurement, and conventions used in this data sheet. Acronyms and Abbreviations Table X lists abbreviations and acronyms used in this data sheet. Table X. Acronyms and Abbreviations Acronym/ Abbreviation Definition A/D ADC CODEC D/A DMA EPB FCS FIFO FIQ GPIO ICT IR IRQ IrDA JTAG LCD LED LQFP LSB MIPS MMU MSB PBGA PCB PDA PLL p/u RISC RTC SIR SRAM SSI analog-to-digital analog-to-digital converter coder / decoder digital-to-analog direct-memory access embedded peripheral bus frame check sequence first in / first out fast interrupt request general purpose I/O in circuit test infrared standard interrupt request Infrared Data Association Joint Test Action Group liquid crystal display light-emitting diode low profile quad flat pack least significant bit millions of instructions per second memory management unit most significant bit plastic ball grid array printed circuit board personal digital assistant phase locked loop pull-up resistor reduced instruction set computer Real-Time Clock slow kbps infrared static random access memory synchronous serial interface Table X. Acronyms and Abbreviations Continued Acronym/ Abbreviation Definition TAP TLB UART test access port translation lookaside buffer universal asynchronous receiver Units of Measurement Table Y. Unit of Measurement Unit of Measure degree Celsius fs Hz kbps KB kHz Mbps MB MBps MHz µA µF µW µs mA mW ms ns V W sample frequency hertz cycle per second kilobits per second kilobyte 1,024 bytes kilohertz kilohm megabits 1,048,576 bits per second megabyte 1,048,576 bytes megabytes per second megahertz 1,000 kilohertz microampere microfarad microwatt microsecond 1,000 nanoseconds milliampere milliwatt millisecond 1,000 microseconds nanosecond volt watt Copyright Cirrus Logic, Inc. 2005 All Rights Reserved DS506F1 EP7311 High-Performance, Low-Power System on Chip General Conventions Hexadecimal numbers are presented with all letters in uppercase and a lowercase “h” appended or with a 0x at the beginning. For example, 0x14 and 03CAh are hexadecimal numbers. Binary numbers are enclosed in single quotation marks when in text for example, ‘11’ designates a binary number . Numbers not indicated by an “h”, 0x or quotation marks are decimal. Registers are referred to by acronym, with bits listed in brackets separated by a colon for example, CODR[7:0] , and are described in the EP7311 User’s Manual. The use of “TBD” indicates values that are “to be determined,” “n/a” designates “not available,” and “n/c” indicates a pin that is a “no connect.” Pin Description Conventions Abbreviations used for signal directions are listed in Table Z. Table Z. Pin Description Conventions Abbreviation Direction Input Output Input or Output DS506F1 Ordering Information Model EP7311-CB EP7311-CB-90 MHz EP7311-IB EP7311-IB-90 MHz EP7311-CV EP7311-IV EP7311-CR EP7311-CR-90 MHz Temperature 0 to +70 °C -40 to +85 °C. 0 to +70 °C -40 to +85 °C. 0 to +70 °C Package 256-pin PBGA, 17mm X 17mm 208-pin LQFP. 204-pin TFBGA, 13mm X 13mm. Environmental, Manufacturing, & Handling Information Model Number EP7311-CB EP7311-CB-90 MHz EP7311-IB EP7311-IB-90 MHz EP7311-CV EP7311-IV EP7311-CR EP7311-CR-90 MHz Peak Reflow Temp 225 °C MSL Rating* 3 * MSL Moisture Sensitivity Level as specified by IPC/JEDEC J-STD-020. Max Floor Life 7 Days Copyright Cirrus Logic, Inc. 2005 All Rights Reserved DS506F1 EP7311 High-Performance, Low-Power System on Chip Date NOV 2003 AUG 2005 Changes First preliminary release. Updated SDRAM timing. Added MSL data. Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries “Cirrus” believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind express or implied . Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE “CRITICAL APPLICATIONS” . CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. SPI is a trademark of Motorola, Inc. Microwire is a trademark of National Semiconductor Corporation. LINUX is a registered trademark of Linus Torvalds. Microsoft Windows and Microsoft are registered trademarks of Microsoft Corporation. DS506F1 Copyright Cirrus Logic, Inc. 2005 All Rights Reserved EP7311 High-Performance, Low-Power System on Chip Copyright Cirrus Logic, Inc. 2005 All Rights Reserved DS506F1

PDF Datasheet Preview

• ARM720T Processor ARM7TDMI CPU 8 KB of four-way set-associative cache MMU with 64-entry TLB Thumb code support enabled
• Ultra low power 90 mW at 74 MHz typical 30 mW at 18 MHz typical 10 mW in the Idle State <1 mW in the Standby State
• 48 KB of on-chip SRAM
• MaverickKey IDs
32-bit unique ID can be used for SDMI compliance 128-bit random ID
• Dynamically programmable clock speeds of 18, 36, 49, and 74 MHz

EP7311 Data Sheet

High-performance, Low-power, System-on-chip
with SDRAM & Enhanced Digital Audio Interface

OVERVIEW

The Maverick EP7311 is designed for ultra-low-power applications such as PDAs, smart cellular phones, and industrial hand held information appliances. The core-logic functionality of the device is built around an ARM720T processor with 8 KB of four-way set-associative unified cache and a write buffer. Incorporated into the ARM720T is an enhanced memory management unit MMU which allows for support of sophisticated operating systems like

BLOCK DIAGRAM
cont.
cont.

SERIAL PORTS

USER INTERFACE

Multimedia Codec Port

Serial Interface

Power Management
2 UARTs w/ IrDA

Boot ROM

Internal Data Bus

EPB Bus

ARM720T

ICE-JTAG

ARM7TDMI CPU Core
8 KB Write Cache Buffer

Bus Bridge

MaverickKeyTM

Memory Controller

SRAM I/F

SDRAM I/F

On-chip SRAM 48 KB

Clocks & Timers

Interrupts, PWM & GPIO

Keypad& Touch

Screen I/F

LCD Controller

MEMORY AND STORAGE

Copyright Cirrus Logic, Inc. 2005 All Rights Reserved

AUG ‘05 DS506F1

EP7311 High-Performance, Low-Power System on Chip

FEATURES cont
256-Ball PBGA Package Specifications 38 256-Ball PBGA Pinout Top View 39 256-Ball PBGA Ball Listing 39 JTAG Boundary Scan Signal Ordering 43

CONVENTIONS 48

Acronyms and Abbreviations 48 Units of Measurement 48 General Conventions 49 Pin Description Conventions 49
Ordering Information 50

Environmental, Manufacturing, & Handling Information 50

Copyright Cirrus Logic, Inc. 2005

All Rights Reserved

DS506F1

List of Figures

EP7311 High-Performance, Low-Power System on Chip

Figure A Maximum EP7309 Based System Figure Legend for Timing Diagrams Figure Static Memory Single Read Cycle Timing Measurement Figure Static Memory Single Write Cycle Timing Measurement Figure Static Memory Burst Read Cycle Timing Measurement Figure Static Memory Burst Write Cycle Timing Measurement Figure SSI1 Interface Timing Measurement Figure SSI2 Interface Timing Measurement Figure LCD Controller Timing Measurement Figure JTAG Timing Measurement Figure 208-Pin LQFP Package Outline Drawing Figure 208-Pin LQFP Low Profile Quad Flat Pack Pin Diagram Figure 204-Ball TFBGA Package Figure 256-Ball PBGA Package

List of Tables
Table Power Management Pin Assignments Table Static Memory Interface Pin Assignments Table Universal Asynchronous Receiver/Transmitters Pin Assignments Table DAI Interface Pin Assignments Table CODEC Interface Pin Assignments Table SSI2 Interface Pin Assignments Table Serial Interface Pin Assignments Table LCD Interface Pin Assignments Table Keypad Interface Pin Assignments Table Interrupt Controller Pin Assignments Table Real-Time Clock Pin Assignments Table PLL and Clocking Pin Assignments Table DC-to-DC Converter Interface Pin Assignments Table General Purpose Input/Output Pin Assignments Table Hardware Debug Interface Pin Assignments Table LED Flasher Pin Assignments Table DAI/SSI2/CODEC Pin Multiplexing Table Pin Multiplexing Table 208-Pin LQFP Numeric Pin Listing Table 204-Ball TFBGA Ball Listing Table 256-Ball PBGA Ball Listing Table JTAG Boundary Scan Signal Ordering Table Acronyms and Abbreviations Table Unit of Measurement Table Pin Description Conventions

DS506F1

Copyright Cirrus Logic, Inc. 2005

All Rights Reserved

EP7311 High-Performance, Low-Power System on Chip

Processor Core - ARM720T

The EP7311 incorporates an ARM 32-bit RISC microcontroller that controls a wide range of on-chip peripherals. The processor utilizes a three-stage pipeline consisting of fetch, decode and execute stages. Key features include:
• ARM 32-bit and Thumb 16-bit compressed instruction sets
• Enhanced MMU for Microsoft Windows CE and other operating systems
• 8 KB of 4-way set-associative cache.
• Translation Look Aside Buffers with 64 Translated Entries

Power Management

The EP7311 is designed for ultra-low-power operation. Its core operates at only V, while its I/O has an operation range of V allowing the device to achieve a performance level equivalent to 60 MIPS. The device has three basic power states:
• Operating This state is the full performance state. All the clocks and peripheral logic are enabled.
• Idle This state is the same as the Operating State, except the CPU clock is halted while waiting for an event such as a key press.
• Standby This state is equivalent to the computer being switched off no display , and the main oscillator shut down. An event such as a key press can wake-up the processor.

Pin Mnemonic

Pin Description

BATOK nEXTPWR nPWRFL nBATCHG

Battery ok input

External power supply sense input

Power fail sense input

Battery changed sense input

Table A. Power Management Pin Assignments

MaverickKey Unique ID

MaverickKey unique hardware programmed IDs are a solution to the growing concern over secure web content and commerce. With Internet security playing an important role in the delivery of digital media such as books or music, traditional software methods are quickly becoming unreliable. The MaverickKey unique IDs provide OEMs with a method of utilizing specific hardware IDs such as those assigned for SDMI Secure Digital Music Initiative or any other authentication mechanism.

Both a specific 32-bit ID as well as a 128-bit random ID is programmed into the EP7311 through the use of laser probing technology. These IDs can then be used to match secure copyrighted content with the ID of the target device the EP7311 is powering, and then deliver the copyrighted information over a secure connection. In addition, secure transactions can benefit by also matching device IDs to server IDs. MaverickKey IDs provide a level of hardware security required for today’s Internet appliances.

Memory Interfaces

There are two main external memory interfaces. The first one is the ROM/SRAM/FLASH-style interface that has programmable wait-state timings and includes burst-mode capability, with six chip selects decoding six 256 MB sections of addressable space. For maximum flexibility, each bank can be specified to be 8-, 16-, or 32-bits wide. This allows the use of 8-bit-wide boot ROM options to minimize overall system cost. The on-chip boot ROM can be used in product manufacturing to serially download system code into system FLASH memory. To further minimize system memory requirements and cost, the ARM Thumb instruction set is supported, providing for the use of high-speed 32-bit operations in 16-bit op-codes and yielding industry-leading code density.

Pin Mnemonic

Pin Description
nCS[5:0] A[27:0] D[31:0] nMOE/nSDCAS nMWE/nSDWE

HALFWORD

WORD WRITE/nSDRAS

Note

Note

O Chip select out

O Address output

I/O Data I/O

O ROM expansion OP enable

O ROM expansion write enable

Halfword access select output
JTAG Boundary Scan Signal Ordering

EP7311 High-Performance, Low-Power System on Chip
Table W. JTAG Boundary Scan Signal Ordering

LQFP TFBGA PBGA

Pin No. Ball

Ball

Signal

Type
nCS[5]

EXPCLK

WORD

WRITE/nSDRAS

RUN/CLKEN

EXPRDY

TXD2

RXD2

PB[7]

PB[6]

PB[5]

PB[4]

PB[3]

PB[2]

PB[1]/PRDY2

PB[0]/PRDY1

PA[7]

PA[6]

PA[5]

PA[4]

PA[3]

PA[2]

PA[1]

PA[0]

LEDDRV

TXD1

PHDIN

RXD1
nTEST1
nTEST0

EINT3
nEINT2
nEINT1

Position
1 3 6 8 10 13 14 16 17 20 23 26 29 32 35 38 41 44 47 50 53 56 59 62 65 67 69 70 71 72 73 74 75 76 77 78
Table W. JTAG Boundary Scan Signal Ordering Continued

LQFP TFBGA PBGA

Pin No. Ball

Ball

Signal

Type Position
nEXTFIQ PE[2]/CLKSEL PE[1]/BOOTSEL1 PE[0]/BOOTSEL0 PD[7]/SDQM[1] PD[6/SDQM[0]]

PD[5] PD[4] PD[3] PD[2] PD[1] PD[0]/LEDFLSH SSIRXFR ADCIN nADCCS DRIVE1 DRIVE0 ADCCLK ADCOUT SMPCLK FB1 FB0 COL7 COL6 COL5 COL4 COL3 COL2 COL1 COL0 BUZ D[31] D[30] D[29] D[28] A[27]/DRA[0] D[27] A[26]/DRA[1]

Copyright Cirrus Logic, Inc. 2005

All Rights Reserved

DS506F1

DS506F1

EP7311 High-Performance, Low-Power System on Chip
Table W. JTAG Boundary Scan Signal Ordering Continued

LQFP TFBGA PBGA

Pin No. Ball

Ball

Signal

Type Position

D[26] A[25]/DRA[2]

D[25] HALFWORD A[24]/DRA[3]

D[24] A[23]/DRA[4]

D[23] A[22]/DRA[5]

D[22] A[21]/DRA[6]

D[21] A[20]/DRA[7]

D[20] A[19]/DRA[8]

D[19] A[18]/DRA[9]

D[18] A[17]/DRA[10]

D[17] A[16]/DRA[11]

D[16] A[15]/DRA[12]

D[15] A[14]/DRA[13]

D[14] A[13]/DRA[14]

D[13] A[12] D[12] A[11] D[11] A[10] D[10] A[9] D[9] A[8] D[8]

Copyright Cirrus Logic, Inc. 2005

All Rights Reserved

EP7311 High-Performance, Low-Power System on Chip
Table W. JTAG Boundary Scan Signal Ordering Continued

LQFP TFBGA PBGA

Pin No. Ball

Ball

Signal

Type Position

A[7] D[7] nBATCHG nEXTPWR BATOK nPOR nMEDCHG/nBROM nURESET WAKEUP nPWRFL A[6] D[6] A[5] D[5] A[4] D[4] A[3] D[3] A[2] D[2] A[1] D[1] A[0] D[0] CL2 CL1 FRM M DD[3] DD[2] DD[1] DD[0] nSDCS[1] nSDCS[0] SDQM[3] SDQM[2] SDCKE SDCLK

Copyright Cirrus Logic, Inc. 2005

All Rights Reserved

DS506F1

EP7311 High-Performance, Low-Power System on Chip
Table W. JTAG Boundary Scan Signal Ordering Continued

LQFP TFBGA PBGA

Pin No. Ball

Ball

Signal

Type Position
nMWE/nSDWE nMOE/nSDCAS
nCS[0] nCS[1] nCS[2] nCS[3] nCS[4]
1 See EP7311 Users’ Manual for pin naming / functionality.
2 For each pad, the JTAG connection ordering is input, output, then enable as applicable.

DS506F1

Copyright Cirrus Logic, Inc. 2005

All Rights Reserved

EP7311 High-Performance, Low-Power System on Chip

CONVENTIONS

This section presents acronyms, abbreviations, units of measurement, and conventions used in this data sheet.

Acronyms and Abbreviations

Table X lists abbreviations and acronyms used in this data sheet.

Table X. Acronyms and Abbreviations

Acronym/ Abbreviation

Definition

A/D ADC CODEC D/A DMA EPB FCS FIFO FIQ GPIO ICT IR IRQ IrDA JTAG LCD LED LQFP LSB MIPS MMU MSB PBGA PCB PDA PLL p/u RISC RTC SIR SRAM SSI
analog-to-digital analog-to-digital converter coder / decoder digital-to-analog direct-memory access embedded peripheral bus frame check sequence first in / first out fast interrupt request general purpose I/O in circuit test infrared standard interrupt request Infrared Data Association Joint Test Action Group liquid crystal display light-emitting diode low profile quad flat pack least significant bit millions of instructions per second memory management unit most significant bit plastic ball grid array printed circuit board personal digital assistant phase locked loop pull-up resistor reduced instruction set computer Real-Time Clock slow kbps infrared static random access memory synchronous serial interface

Table X. Acronyms and Abbreviations Continued

Acronym/ Abbreviation

Definition

TAP TLB UART
test access port translation lookaside buffer universal asynchronous receiver

Units of Measurement

Table Y. Unit of Measurement

Unit of Measure
degree Celsius
fs Hz kbps KB kHz Mbps MB MBps MHz µA µF µW µs mA mW ms ns V W
sample frequency hertz cycle per second kilobits per second kilobyte 1,024 bytes kilohertz kilohm megabits 1,048,576 bits per second megabyte 1,048,576 bytes megabytes per second megahertz 1,000 kilohertz microampere microfarad microwatt microsecond 1,000 nanoseconds milliampere milliwatt millisecond 1,000 microseconds nanosecond volt watt

Copyright Cirrus Logic, Inc. 2005

All Rights Reserved

DS506F1

EP7311 High-Performance, Low-Power System on Chip

General Conventions

Hexadecimal numbers are presented with all letters in uppercase and a lowercase “h” appended or with a 0x at the beginning. For example, 0x14 and 03CAh are hexadecimal numbers. Binary numbers are enclosed in single quotation marks when in text for example, ‘11’ designates a binary number . Numbers not indicated by an “h”, 0x or quotation marks are decimal.

Registers are referred to by acronym, with bits listed in brackets separated by a colon for example, CODR[7:0] , and are described in the EP7311 User’s Manual. The use of “TBD” indicates values that are “to be determined,” “n/a” designates “not available,” and “n/c” indicates a pin that is a “no connect.”

Pin Description Conventions

Abbreviations used for signal directions are listed in Table Z.

Table Z. Pin Description Conventions

Abbreviation

Direction

Input

Output

Input or Output

DS506F1
Ordering Information

Model EP7311-CB EP7311-CB-90 MHz EP7311-IB EP7311-IB-90 MHz EP7311-CV EP7311-IV EP7311-CR EP7311-CR-90 MHz

Temperature 0 to +70 °C
-40 to +85 °C. 0 to +70 °C -40 to +85 °C. 0 to +70 °C

Package 256-pin PBGA, 17mm X 17mm
208-pin LQFP. 204-pin TFBGA, 13mm X 13mm.

Environmental, Manufacturing, & Handling Information

Model Number EP7311-CB EP7311-CB-90 MHz EP7311-IB EP7311-IB-90 MHz EP7311-CV EP7311-IV EP7311-CR EP7311-CR-90 MHz

Peak Reflow Temp 225 °C

MSL Rating* 3
* MSL Moisture Sensitivity Level as specified by IPC/JEDEC J-STD-020.

Max Floor Life 7 Days

Copyright Cirrus Logic, Inc. 2005

All Rights Reserved

DS506F1

EP7311 High-Performance, Low-Power System on Chip

Date NOV 2003 AUG 2005

Changes First preliminary release. Updated SDRAM timing. Added MSL data.

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DS506F1

Copyright Cirrus Logic, Inc. 2005

All Rights Reserved

EP7311 High-Performance, Low-Power System on Chip

Copyright Cirrus Logic, Inc. 2005

All Rights Reserved

DS506F1

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived EP7311-IV-90 Datasheet file may be downloaded here without warranties.

Datasheet ID: EP7311-IV-90 523226