CS61584A-IQ3ZR

CS61584A-IQ3ZR Datasheet


CS61584A

Part Datasheet
CS61584A-IQ3ZR CS61584A-IQ3ZR CS61584A-IQ3ZR (pdf)
Related Parts Information
CS61584A-IQ5Z CS61584A-IQ5Z CS61584A-IQ5Z
CS61584A-IQ5ZR CS61584A-IQ5ZR CS61584A-IQ5ZR
CS61584A-IQ3Z CS61584A-IQ3Z CS61584A-IQ3Z
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CS61584A

DDuuaall TT11//EE11 LLiinnee IInntteerrffaaccee
l Dual T1/E1 Line Interface l Volt and 5 Volt Versions l Crystal-less Jitter Attenuator Meets

European CTR 12 and ETSI ETS 300 011 Specifications l Matched Impedance Transmit Drivers l Transmitter Tri-state Capability l Common Transmit and ReceiveTransformers for all Modes l Serial and Parallel Host Mode Operation l User-customizable Pulse Shapes l Supports JTAG Boundary Scan l Compliant with:

ITU-T Recommendations G.703, G.704, G.706, G.732, G.775 and I.431

American National Standards ANSI T1.102, T1.105, T1.403, T1.408, and T1.231

FCC Rules and Regulations Part 68 and Part 15

AT&T Publication 62411 ETSI ETS 300 011, 300 233, CTR 12, TBR 13
l TR-NET-00499 Description

The CS61584A is a dual line interface for T1/E1 applications, designed for high-volume cards where low power and high density are required. The device is optimized for flexible microprocessor control through a serial or parallel Host mode interface. Hardware mode operation is also available.

Matched impedance drivers reduce power consumption and provide substantial transmitter return loss. The transmitter pulse shapes are customizable to allow nonstandard line loads. Crystalless jitter attenuation complies with most stringent standards. Support of JTAG boundary scan enhances system testability and reliability.
ORDERING INFORMATION See page CS61584A-IQ3:3.3V, 64-pin TQFP, -40 to +85° C CS61584A-IL5:5.0V, 68-pin PLCC, -40 to +85° C CS61584A-IQ5:5.0V, 64-pin TQFP, -40 to +85° C

Serial Port Parallel Port Hardware Mode

IPOL P/S

INT SCLK SDO SDI SPOL

IPOL DTACK P/S

INT RD DS AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 ALE AS WR R/W BTS

CLKE ATTEN0 ATTEN1 RLOOP1 RLOOP2 LLOOP TAOS1 TAOS2 CON01 CON02 CON11 CON12 CON21 CON22 CON31 CON32

TCLK1 TDATA1 TPOS1

AIS1 TNEG1 RCLK1

RDATA1 RPOS1 BPV1 RNEG1

TCLK2 TDATA2 TPOS2

AIS2 TNEG2 RCLK2

RDATA2 RPOS2 BPV2 RNEG2

E N C O D E R

D E C O D E R

E N C O D E R

D E C O D E R

JTAG 4

CONTROL

R E M O T E

JITTER

ATTENUATOR

R E M O T E

JITTER

ATTENUATOR

CLOCK GENERATOR

REFCLK XTALOUT 1XCLK

PULSE

TAOS

SHAPING

DRIVER

CIRCUITRY

LOS &

CLOCK &

DATA

RECEIVER

DETECT

RECOVERY

PULSE

TAOS

SHAPING
Boundary Scan Register The BSR is connected in parallel to all the digital I/O pins, and provides the mechanism for applying/reading test patterns to/from the board traces. The BSR is 62 bits long and is initialized and read using the instruction SAMPLE/PRELOAD. The bit ordering for the BSR is the same as the top-view package pin out, beginning with the LOS1 pin and moving counterclockwise to end with the PD1 pin as shown in Table Note that the analog, oscillator, power, ground, CLKE/IPOL, and MODE pins are not included as part of the boundary-scan register.

The input pins require one bit in the BSR and only one J-TCK cycle is required to load test data for each input pin.

The output pins have two bits in the BSR to define output high, output low, or high impedance. The first bit shifted in first selects between an outputenabled state bit set to 1 or high-impedance state bit set to The second bit shifted in contains the test data that may be output on the pin. Therefore, two J-TCK cycles are required to load test data for each output pin.

The bi-directional pins have three bits in the BSR to define input, output high, output low, or high impedance. The first bit shifted into the BSR configures the output driver as high-impedance bit set to 0 or active bit set to The second bit shifted into the BSR sets the output value when the first bit is The third bit captures the value of the pin. This pin may have its value set externally as an input if the first bit is 0 or set internally as an output if the first bit is To configure a pad as an input, the JTDI pattern is 0X0. To configure a pad as an output, the J-TDI pattern is 1X1. Therefore, three JTCK cycles are required to load test data for each bi-directional pin.

When JTAG testing is conducted in Host mode, the polarity of the INT pin is determined by the state of the IPOL pin. The JTAG BSR should configure the INT pin as an input in Hardware mode and as an output in Host mode.

BSR Bits 0-2 3-5 6 7 8-9
10 - 11 12 - 13
14 15 - 17
18 19 - 21 22 - 24 25 - 27 28 - 30 31 - 33 34 - 36 37 - 39 40 - 42
43 44 45 - 46 47 - 48 49 - 50 51 52 53 - 55 56 - 58 59 60 61

Pin Name LOS1, SAD6 TNEG1, AIS1 TPOS1, TDATA1

TCLK1 RNEG1, BPV1 RPOS1, RDATA1

RCLK1 ATTEN1, CS RLOOP1, INT RLOOP2, SCLK, RD DS LLOOP, SDO, AD0 TAOS1, SDI, AD1 TAOS2, SPOL, AD2 CON01, AD3 CON02, AD4 CON11, AD5 CON12, AD6 CON21, AD7 CON22, ALE AS CON31, WR R/W

RCLK2 RPOS2, RDATA2

RNEG2, BPV2 TCLK2

TPOS2, TDATA2 TNEG2, AIS2 LOS2, SAD7 CON32, BTS PD2, SAD5 PD1, SAD4

Pad Type bi-directional bi-directional
input output input bi-directional input bi-directional bi-directional bi-directional bi-directional bi-directional bi-directional bi-directional bi-directional input output input bi-directional bi-directional input

Table Boundary Scan Register

DDS2S6216P1PF15

DS261PP5

CS61584A
31 28 27
12 11
4 bits
16 bits
11 bits

BIT # s 31-28 27-14 13-12 11-1 0

Function Version Number Part Number Derivative Code Manufacturer Number Constant Logic ‘1’

Total Bits 4 14 2 11 1

Table Device Identification Register

Bypass Register The Bypass register consists of a single bit, and provides a serial path between J-TDI and J-TDO, bypassing the BSR. This allows bypassing specific devices during certain board-level tests. This also reduces test access times by reducing the total number of shifts required from J-TDI to J-TDO.

JTAG Instructions and Instruction Register IR

The instruction register 2 bits allows the instruction to be shifted into the JTAG circuit. The instruction selects the test to be performed or the data register to be accessed or both. The valid instructions are shifted in LSB first and are listed in Table 12:

IR CODE 00 01 10 11

INSTRUCTION EXTEST SAMPLE/PRELOAD IDCODE BYPASS

Table

EXTEST Instruction The EXTEST instruction allows testing of off-chip circuitry and board-level interconnect. EXTEST connects the BSR to the JTDI and J-TDO pins. The normal path between the CS61584A logic and I/O pins is broken. The signals on the output pins are loaded from the BSR and the signals on the input pins are loaded into the BSR.

SAMPLE/PRELOAD Instruction The SAMPLE/PRELOAD instructions allows scanning of the boundary-scan register without interfering with the operation of the CS61584A. This instruction connects the BSR to the J-TDI and J-TDO pins. The normal path between the CS61584A logic and its I/O pins is maintained. The signals on the I/O pins are loaded into the BSR. Additionally, this instruction can be used to latch values into the digital output pins.

IDCODE Instruction The IDCODE instruction connects the device identification register to the JTDO pin. The IDCODE instruction is forced into the instruction register during the Test-Logic-Reset controller state.The default instruction is IDCODE after a device reset.

BYPASS Instruction The BYPASS instruction connects the minimum length bypass register between the J-TDI and J-TDO pins and allows data to be shifted in the Shift-DR controller state.
ORDERING INFORMATION

Model CS61584A-IL3 CS61584A-IL5 CS61584A-IQ3 CS61584A-IQ3Z Lead Free CS61584A-IQ5 CS61584A-IQ5Z Lead Free

Operating Voltage V

Package 68-pin PLCC
64-pin LQFP

Temperature -40 to +85 °C

ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION

Model Number CS61584A-IL3 CS61584A-IL5 CS61584A-IQ3 CS61584A-IQ3Z Lead Free CS61584A-IQ5 CS61584A-IQ5Z Lead Free

Peak Reflow Temp
225 °C
240 °C 250 °C 240 °C 250 °C

MSL Rating* 3

Max Floor Life 7 Days
* MSL Moisture Sensitivity Level as specified by IPC/JEDEC J-STD-020.

DS261F1

CS61584A

Date JAN 2001 SEP 2005
Changes Preliminary Release Updated device ordering info. Updated legal notice. Added MSL data..

Contacting Cirrus Logic Support

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IMPORTANT NOTICE

Cirrus Logic, Inc. and its subsidiaries “Cirrus” believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind express or implied . Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.

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Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.

DS261F1
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Datasheet ID: CS61584A-IQ3ZR 523208