PEX8606BA-AIC4U1DRDK

PEX8606BA-AIC4U1DRDK Datasheet

PEX 8606 General Features

Part	Datasheet
PEX8606BA-AIC4U1DRDK	PEX8606BA-AIC4U1DRDK (pdf)

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Version 2010 PEX 8606 General Features o 6-lane PCI Express switch - Integrated GT/s SerDes o Up to 6 configurable ports o 15 x 15mm2, 196-ball PBGA o Typical Power Watts PEX 8606 Key Features o Standards Compliant - PCI Express Base Specification r2.0 Backwards compatible with PCIe r1.0a/1.1 - PCI Power Management Spec r1.2 - Microsoft Vista Compliant - Supports Access Control Services - Dynamic link-width control - Dynamic SerDes Speed Control o High Performance - Non-blocking internal architecture - Full line rate on all ports - Cut-Thru latency 190ns - 2KB max payload size - Read Pacing intelligent bandwidth allocation - Dual Cast o Dual-Host & Fail-Over Support - Configurable Non-Transparent port - Moveable upstream port - Crosslink port capability o PCI Express Power Management - Link power management states L0, L0s, L1, L2/L3 Ready, and L3 - Device states D0 and D3hot o Spread Spectrum Clock Isolation - Dual clock domain o Quality of Service QoS - Two Virtual Channels VC per port - Eight Traffic Classes per port - Weighted Round-Robin Port & VC Arbitration o Reliability, Availability, Serviceability - All ports Hot-Plug capable thru I2C Hot-Plug Controller on every port - ECRC & Poison bit support - Data path protection - Memory RAM error correction - Advanced Error Reporting support - Port Status bits and GPIO available - Per port error diagnostics - Performance monitoring per port payload & header counters - JTAG AC/DC boundary scan - Fatal Error FATAL_ERR# output signal - INTA# output signal PEX 8606 PCIe Gen2, GT/s 6-lane 6-port PCI Switch The ExpressLane PEX 8606 device offers PCI Express switching capability enabling users to add scalable high bandwidth non-blocking interconnection to a wide variety of applications including communications platforms, control plane applications and embedded systems. The PEX 8606 is well suited for fan-out, aggregation, peer-to-peer, and intelligent I/O module applications. Low Packet Latency & High Performance The PEX 8606 architecture supports packet cut-thru with a maximum latency of 190ns in x1 to x1 configuration. This, combined with large packet memory and non-blocking internal switch architecture, provides full line rate on all ports for lowlatency applications such as communications and embedded. The low latency enables applications to achieve high throughput and performance. In addition to low latency, the device supports a max payload size of 2048 bytes, enabling the user to achieve even higher throughout. Data Integrity The PEX 8606 provides end-to-end CRC protection ECRC and Poison bit support to enable designs that require guaranteed error-free packets. PLX also supports data path parity and memory RAM error correction as packets pass through the switch. Dual-Host and Fail-Over Support The PEX 8606 supports full non-transparent bridging NTB functionality to allow implementation of multi-host systems and intelligent I/O modules in applications which require redundancy support such as communications, storage, and servers. Non-transparent bridges allow systems to isolate host memory domains by presenting the processor subsystem as an endpoint rather than another memory system. Base address registers are used to translate addresses doorbell registers are used to send interrupts between the address domains and scratchpad registers are accessible from both address domains to allow inter-processor communication. Device Operation Configuration Flexibility The PEX 8606 provides several ways to configure its operations. The device can be configured through strapping pins, I2C interface, CPU configuration cycles and/or an optional serial EEPROM. This allows for easy debug during the development phase and functional monitoring during the operation phase. Flexible Port Configurations The PEX 8606 supports the port configurations as shown in figure 1 below. The figure shows a 6-port configuration and a 5-port configuration. Figure Port Configurations Hot-Plug for High Availability Hot-Plug capability allows users to replace hardware modules and perform maintenance without powering down the system. The PEX 8606 Hot-Plug capability feature makes it suitable for High Availability HA applications. If the PEX 8606 is used in an application where one or more of its downstream ports connect to PCI Express slots, each port’s Hot-Plug Controller can be used to manage the Hot-Plug event of its associated slot. Every port on the PEX 8606 is equipped with a Hot-Plug control/status register to support Hot-Plug capability through external logic via the I2C interface. Dual Cast The PEX 8606 supports Dual Cast, a feature which allows for the copying of data e.g. packets from one ingress port to two egress ports allowing for higher performance in storage, security, and mirroring applications. Read Pacing The Read Pacing feature allows users to throttle the amount of read requests being made by downstream devices. In the case where a downstream device requests several long reads backto-back, the Root Complex gets tied up in serving this downstream port. If this port has a narrow link and is therefore slow in receiving these read packets from the Root Complex, then other downstream ports may become starved thus, impacting performance. The Read Pacing feature enhances performances by allowing for the adequate servicing of all downstream devices by intelligent handling of read requests. SerDes Power and Signal Management The PEX 8606 provides low power capability that is fully compliant with the PCI Express power management specification. In addition, the SerDes physical links can be turned off when unused for even lower power. The PEX 8606 supports software control of the SerDes outputs to allow optimization of power and signal strength in a system. The PLX SerDes implementation supports four levels of power off, low, typical, and high. The SerDes block also supports loop-back modes and advanced reporting of error conditions, which enables efficient debug and management of the entire system. Port and Virtual Channel VC Arbitration The PEX 8606 switch supports hardware fixed and Weighted Round-Robin WRR Ingress Port Arbitration. This allows fine tuning of Quality of Service and efficient use of packet buffers for better system performance. The PEX 8606 also supports WRR VC arbitration scheme between the two virtual channels. Suitable for fan-out, control plane applications, embedded systems as well as intelligent I/O and host isolation applications, PEX 8606 can be configured for a wide variety of form factors and applications. Fan-Out The PEX 8606 switch, with its high port count and flexible configurations, allows user specific tuning to a variety of hostcentric as well as peer-to-peer applications. Figure Fan-in/out Usage Figure 2 shows a typical fan-out design, where the processor provides a PCI Express link that needs to be fanned into a larger number of smaller ports for a variety of I/O functions, each with different bandwidth requirements. In this example, the PEX 8606 would typically have a 1-lane upstream port, and as many as 5 downstream ports. The downstream ports provide x1 PCI Express connectivity to the endpoints. With its six ports, the PEX 8606 can provide fanout connectivity to up to five PCI Express devices. The figure also shows how some of the ports can be bridged to provide PCI slots or Generic devices through the use of the PEX 8311 and PEX 8112 PCIe bridging devices. Docking Station Application The PEX 8606 is ideal for IO expansion applications. The support for SSC isolation as well as its low power consumption makes it an ideal candidate for peripheral expansion. Figure 3 below shows a block diagram for a docking station. With PCI Express slots, the IO subsystem can be expanded in order to extend the peripheral capabilities of a notebook PC. Intelligent Adapter Card The PEX 8606 supports the non-transparency feature. Figure 6 illustrates a host system using an intelligent adapter card. Figure Docking Station Control Planes for Large Systems Control for larger systems can be accomplished with a bigger switch. However, in many cases where multiple PCIe ports are available on the CPU, multiple switches can be used in order to balance the traffic as shown in Figure Figure Control Planes for Large Systems Embedded Control Planes The PEX 8606 is well suited for embedded control plane applications. An example of such application is a packet processing module, as shown in Figure In this example, the FPGAs and ASICs implement an x1 PCI Express Interface. With its high port count, the PEX 8606 can provide connectivity to a high number of FPGAs and ASICs for a robust packet processing communications sub-system. Figure Intelligent Adapter Usage In this figure, the CPU on the Mezzanine card is isolated from the host CPU. The PEX 8606 non-transparent port allows the two CPUs to be isolated but communicate with each other through various registers that are designed in the PEX 8606 for that purpose. The host CPU can dynamically re-assign both the upstream port and the non-transparent port of PEX 8606 allowing the system to be reconfigured. Active-Standby Failover Model The PEX 8606 supports applications requiring dual host, host failover applications through the non-transparency feature. Figure 7 illustrates a dual host system with an active and standby processor configuration. The redundancy of the host and the fabric can be achieved through many possible configurations using NTB function of PEX In the configuration shown below Processor A is the primary active host of the PCI Express system. Processor B acts as the backup Host. In the case of a failure on Processor A, application software is instructed to migrate the PCI Express system to Processor B. Consequently, Processor B becomes the active host and Processor A can be replaced as the backup Host. Product Ordering Information Part Number PEX8606-BA50BC PEX8606-BA50BC G PEX8606-BA50BI G PEX 8606bA-AIC1U1D RDK Description 6 Lane, 6 Port PCIe Switch, 196-ball PBGA 15x15mm2 pkg 6 Lane, 6 Port PCIe Switch, 196-ball PBGA 15x15mm2 pkg, Pb-free 6 Lane, 6 Port PCIe Switch, 196-ball PBGA 15x15mm2 pkg, Pb-free Industrial Temperature PEX 8606 Rapid Development Kit Please visit the PLX Web site at or contact PLX sales at 408-774-9060 for sampling. 2010 by PLX Technology, Inc. All rights reserved. PLX and the PLX logo are registered trademarks of PLX Technology, Inc. ExpressLane is a trademark of PLX Technology, Inc., which may be registered in some jurisdiction. All other product names that appear in this material are for identification purposes only and are acknowledged to be trademarks or registered trademarks of their respective companies. Information supplied by PLX is believed to be accurate and reliable, but PLX Technology, Inc. assumes no responsibility for any errors that may appear in this material. PLX Technology, Inc. reserves the right, without notice, to make changes in product design or specification. PEX8606-SIL-PB-1.3 4/10

PDF Datasheet Preview

Version 2010

PEX 8606 General Features
o 6-lane PCI Express switch - Integrated GT/s SerDes
o Up to 6 configurable ports o 15 x 15mm2, 196-ball PBGA o Typical Power Watts

PEX 8606 Key Features
o Standards Compliant - PCI Express Base Specification r2.0 Backwards compatible with PCIe r1.0a/1.1 - PCI Power Management Spec r1.2 - Microsoft Vista Compliant - Supports Access Control Services - Dynamic link-width control - Dynamic SerDes Speed Control
o High Performance - Non-blocking internal architecture - Full line rate on all ports - Cut-Thru latency 190ns - 2KB max payload size - Read Pacing intelligent bandwidth allocation - Dual Cast
o Dual-Host & Fail-Over Support - Configurable Non-Transparent port - Moveable upstream port - Crosslink port capability
o PCI Express Power Management - Link power management states L0, L0s, L1, L2/L3 Ready, and L3 - Device states D0 and D3hot
o Spread Spectrum Clock Isolation - Dual clock domain
o Quality of Service QoS - Two Virtual Channels VC per port - Eight Traffic Classes per port - Weighted Round-Robin Port & VC Arbitration
o Reliability, Availability, Serviceability - All ports Hot-Plug capable thru I2C Hot-Plug Controller on every port - ECRC & Poison bit support - Data path protection - Memory RAM error correction - Advanced Error Reporting support - Port Status bits and GPIO available - Per port error diagnostics - Performance monitoring per port payload & header counters - JTAG AC/DC boundary scan - Fatal Error FATAL_ERR# output signal - INTA# output signal

PEX 8606

PCIe Gen2, GT/s 6-lane 6-port PCI Switch

The ExpressLane PEX 8606 device offers PCI Express switching capability enabling users to add scalable high bandwidth non-blocking interconnection to a wide variety of applications including communications platforms, control plane applications and embedded systems. The PEX 8606 is well suited for fan-out, aggregation, peer-to-peer, and intelligent I/O module applications.

Low Packet Latency & High Performance The PEX 8606 architecture supports packet cut-thru with a maximum latency of 190ns in x1 to x1 configuration. This, combined with large packet memory and non-blocking internal switch architecture, provides full line rate on all ports for lowlatency applications such as communications and embedded. The low latency enables applications to achieve high throughput and performance. In addition to low latency, the device supports a max payload size of 2048 bytes, enabling the user to achieve even higher throughout.

Data Integrity The PEX 8606 provides end-to-end CRC protection ECRC and Poison bit support to enable designs that require guaranteed error-free packets. PLX also supports data path parity and memory RAM error correction as packets pass through the switch.

Dual-Host and Fail-Over Support The PEX 8606 supports full non-transparent bridging NTB functionality to allow implementation of multi-host systems and intelligent I/O modules in applications which require redundancy support such as communications, storage, and servers.

Non-transparent bridges allow systems to isolate host memory domains by presenting the processor subsystem as an endpoint rather than another memory system. Base address registers are used to translate addresses doorbell registers are used to send interrupts between the address domains and scratchpad registers are accessible from both address domains to allow inter-processor communication.

Device Operation Configuration Flexibility The PEX 8606 provides several ways to configure its operations. The device can be configured through strapping pins, I2C interface, CPU configuration cycles and/or an optional serial EEPROM. This allows for easy debug during the development phase and functional monitoring during the operation phase.

Flexible Port Configurations The PEX 8606 supports the port configurations as shown in figure 1 below. The figure shows a 6-port configuration and a 5-port configuration.

Figure Port Configurations

Hot-Plug for High Availability Hot-Plug capability allows users to replace hardware modules and perform maintenance without powering down the system. The PEX 8606 Hot-Plug capability feature makes it suitable for High Availability HA applications. If the PEX 8606 is used in an application where one or more of its downstream ports connect to PCI Express slots, each port’s Hot-Plug Controller can be used to manage the Hot-Plug event of its associated slot. Every port on the PEX 8606 is equipped with a Hot-Plug control/status register to support Hot-Plug capability through external logic via the I2C interface.

Dual Cast The PEX 8606 supports Dual Cast, a feature which allows for the copying of data e.g. packets from one ingress port to two egress ports allowing for higher performance in storage, security, and mirroring applications.

Read Pacing The Read Pacing feature allows users to throttle the amount of read requests being made by downstream devices. In the case where a downstream device requests several long reads backto-back, the Root Complex gets tied up in serving this downstream port. If this port has a narrow link and is therefore slow in receiving these read packets from the Root Complex, then other downstream ports may become starved thus, impacting performance. The Read Pacing feature enhances performances by allowing for the adequate servicing of all downstream devices by intelligent handling of read requests.

SerDes Power and Signal Management The PEX 8606 provides low power capability that is fully compliant with the PCI Express power management specification. In addition, the SerDes physical links can be turned off when unused for even lower power. The PEX 8606 supports software control of the SerDes outputs to allow
optimization of power and signal strength in a system. The PLX SerDes implementation supports four levels of power off, low, typical, and high. The SerDes block also supports loop-back modes and advanced reporting of error conditions, which enables efficient debug and management of the entire system.

Port and Virtual Channel VC Arbitration The PEX 8606 switch supports hardware fixed and Weighted Round-Robin WRR Ingress Port Arbitration. This allows fine tuning of Quality of Service and efficient use of packet buffers for better system performance. The PEX 8606 also supports WRR VC arbitration scheme between the two virtual channels.

Suitable for fan-out, control plane applications, embedded systems as well as intelligent I/O and host isolation applications, PEX 8606 can be configured for a wide variety of form factors and applications.

Fan-Out The PEX 8606 switch, with its high port count and flexible configurations, allows user specific tuning to a variety of hostcentric as well as peer-to-peer applications.

Figure Fan-in/out Usage Figure 2 shows a typical fan-out design, where the processor provides a PCI Express link that needs to be fanned into a larger number of smaller ports for a variety of I/O functions, each with different bandwidth requirements. In this example, the PEX 8606 would typically have a 1-lane upstream port, and as many as 5 downstream ports. The downstream ports provide x1 PCI Express connectivity to the endpoints. With its six ports, the PEX 8606 can provide fanout connectivity to up to five PCI Express devices. The figure also shows how some of the ports can be bridged to provide PCI slots or Generic devices through the use of the PEX 8311 and PEX 8112 PCIe bridging devices.

Docking Station Application

The PEX 8606 is ideal for IO expansion applications. The support for SSC isolation as well as its low power consumption makes it an ideal candidate for peripheral expansion. Figure 3 below shows a block diagram for a docking station. With PCI Express slots, the IO subsystem can be expanded in order to extend the peripheral capabilities of a notebook PC.

Intelligent Adapter Card

The PEX 8606 supports the non-transparency feature. Figure 6 illustrates a host system using an intelligent adapter card.

Figure Docking Station Control Planes for Large Systems Control for larger systems can be accomplished with a bigger switch. However, in many cases where multiple PCIe ports are available on the CPU, multiple switches can be used in order to balance the traffic as shown in Figure

Figure Control Planes for Large Systems Embedded Control Planes The PEX 8606 is well suited for embedded control plane applications. An example of such application is a packet processing module, as shown in Figure In this example, the FPGAs and ASICs implement an x1 PCI Express Interface. With its high port count, the PEX 8606 can provide connectivity to a high number of FPGAs and ASICs for a robust packet processing communications sub-system.

Figure Intelligent Adapter Usage

In this figure, the CPU on the Mezzanine card is isolated from the host CPU. The PEX 8606 non-transparent port allows the two CPUs to be isolated but communicate with each other through various registers that are designed in the PEX 8606 for that purpose. The host CPU can dynamically re-assign both the upstream port and the non-transparent port of PEX 8606 allowing the system to be reconfigured.

Active-Standby Failover Model The PEX 8606 supports applications requiring dual host, host failover applications through the non-transparency feature. Figure 7 illustrates a dual host system with an active and standby processor configuration.

The redundancy of the host and the fabric can be achieved through many possible configurations using NTB function of PEX In the configuration shown below Processor A is the primary active host of the PCI Express system. Processor B acts as the backup Host. In the case of a failure on Processor A, application software is instructed to migrate the PCI Express system to Processor B. Consequently, Processor B becomes the active host and Processor A can be replaced as the backup Host.
Product Ordering Information

Part Number PEX8606-BA50BC PEX8606-BA50BC G

PEX8606-BA50BI G

PEX 8606bA-AIC1U1D RDK

Description 6 Lane, 6 Port PCIe Switch, 196-ball PBGA 15x15mm2 pkg 6 Lane, 6 Port PCIe Switch, 196-ball PBGA 15x15mm2 pkg, Pb-free 6 Lane, 6 Port PCIe Switch, 196-ball PBGA 15x15mm2 pkg, Pb-free

Industrial Temperature

PEX 8606 Rapid Development Kit

Please visit the PLX Web site at or contact PLX sales at 408-774-9060 for sampling.
2010 by PLX Technology, Inc. All rights reserved. PLX and the PLX logo are registered trademarks of PLX Technology, Inc. ExpressLane is a trademark of PLX Technology, Inc., which may be registered in some jurisdiction. All other product names that appear in this material are for identification purposes only and are acknowledged to be trademarks or registered trademarks of their respective companies. Information supplied by PLX is believed to be accurate and reliable, but PLX Technology, Inc. assumes no responsibility for any errors that may appear in this material. PLX Technology, Inc. reserves the right, without notice, to make changes in product design or specification.

PEX8606-SIL-PB-1.3
4/10

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