PEX8533-AA25BI G

PEX8533-AA25BI G Datasheet

PEX 8533 General Features

Part	Datasheet
PEX8533-AA25BI G	PEX8533-AA25BI G (pdf)

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Version 2008 PEX 8533 General Features o 32-lane PCI Express switch - Integrated SerDes o Up to six configurable ports o 35mm x 35mm, 680-ball PBGA package o Pin Compatible with PEX 8532 o Typical Power Watts PEX 8533 Key Features o Standards Compliant - PCI Express Base Specification, r1.1 - PCI SHPC Specification, r1.0 o High Performance - Cut-through with 120ns packet latency - Max Payload Size of 1024 Bytes - Non-blocking switch fabric - Full line rate on all ports o PCI Express Power Management - Link power management states L0, L0s, L1, L2/L3 Ready, and L3 - Device states D0 and D3hot o Quality of Service QoS - Eight Traffic Classes per port - Round robin and weighted RR port arbitration o Reliability, Availability, Serviceability - 3 Standard Hot-Plug Controllers - Upstream port as hot-plug client - Transaction Layer end-to-end CRC - Poison bit - INTA & FATAL ERROR signal support - Advanced Error Reporting in addition to PCIe baseline error reporting - Port Status bits and GPO available - Per port performance monitoring • Average packet size, number of packets, CRC errors - JTAG boundary scan PEX 8533 Flexible & Versatile PCI Express Switch Multi-Purpose, Feature Rich PCI Express ExpressLane Switch Highly Flexible Port Configurations The ExpressLaneTM PEX 8533 offers highly configurable ports. There are a maximum of 6 ports that can be configured to any legal width from x1 to x16, in any combination to support your specific bandwidth needs. The ports can be symmetric each port having the same lane width or asymmetric ports having different lane widths . Any of the ports can be designated as the upstream port, which can be changed dynamically. High Performance The ExpressLaneTM PEX 8533 architecture supports packet cut-through with a latency of 115ns x8 to x8 . This, combined with large packet memory 256 to 1024 byte maximum payload size and non-blocking internal switch architecture, provide full line rate on its ports for performance hungry applications such as storage servers or storage switch fabrics. End-to-End Packet Integrity The ExpressLaneTM PEX 8533 provides optional end-to-end CRC protection ECRC and Poison bit support to enable designs that require guaranteed error-free packets. Configuration Flexibility The ExpressLaneTM PEX 8533 provides several ways to configure its operations. The device can be configured through strapping pins, I2C interface, CPU configuration cycles, or an optional serial EEPROM. This allows for easy debug during the development phase, performance monitoring during the operation phase, and driver or software upgrade. Low Power with Granular SerDes Control The ExpressLaneTM PEX 8533 provides low power capability that is fully compliant with the PCI Express power management specification. In addition, the SerDes physical links can be turned off when unused for even lower power. PLX Confidential Flexible Port Width Configuration The lane width of each port can be individually configured through auto-negotiation, hardware strapping, host software configuration, I2C interface, or through an optional EEPROM. The PEX 8533 supports a large number of port configurations. For example, if you are using the PEX 8533 in a fan-out application, you may configure the upstream port as a x8 and the downstream as one x8 port & four x4 ports two x8 & two x4 ports or other combinations, as long as you don’t run out of lanes 32 or ports For a dual-graphics application, you may configure the device as one x16 upstream and two x8 downstream ports see Figure The device can also support x2 & x1 ports by auto-negotiating its x4 ports to the width of the actual end-device it is interfacing with. application where one or more of its downstream ports connect to PCI Express slots, the ports with the Hot Plug Controller feature can be used for these slots. The device will automatically manage the hot-plug event of its hotplug capable ports/slots. Furthermore, the hot-plug capable ports can be used as a hot-plug client or master, allowing it to be used on hot-pluggable carrier modules, backplanes, and fabric modules. Fully Compliant Power Management For applications that require power management, the PEX 8533 device supports both link L0, L0s, L1, L2/L3 Ready, and L3 and device D0 and D3hot power management states, in compliance with the PCI Express power management specification. SerDes Power and Signal Management The ExpressLane PEX 8533 supports software control of the SerDes outputs to allow optimization of power and signal strength in a system. The PLX SerDes implementation supports four levels of power off, low, typical and high. The SerDes block also supports loopback modes and advanced reporting of error conditions, which enables efficient debug and management of the entire system. Figure Port Flexibility Low Packet Latency The PEX 8533 supports packet cut-through with a latency of 115ns between symmetric x8 ingress and egress ports. The low latency enables many applications to achieve high throughput and performance. In addition to low latency, the device supports a packet payload size of up to 1024 bytes, enabling the user to achieve even higher throughput. Hot Plug for High Availability Hot plug capability allows users to replace hardware modules and perform maintenance without powering down the system. The ExpressLane PEX 8533 hot plug capabilities and Advanced Error Reporting features make them suitable for high availability HA applications. Three of the six ports include a Standard Hot Plug Controller. If the PEX 8533 is used in an Suitable for host-centric as well as peer-to-peer traffic patterns, the PEX 8533 can be configured for a wide variety of form factors and applications. Host Centric Fan-out The ExpressLane PEX 8533 device, with its versatile symmetric or asymmetric lane configuration capability, allows for user specific tuning to a variety of hostcentric applications. Figure Fan-in/out Usage PLX Confidential Figure 2 shows a typical server-based design, where the Root Complex provides a PCI Express link that needs to be expanded into a larger number of smaller ports for a variety of I/O functions, each with different bandwidth requirements. In this example, the ExpressLane PEX 8533 would typically have an 8-lane upstream port, and as many as 5 downstream ports. The downstream ports can be of differing widths if required. Peer-to-Peer & Backplane Usage The PEX 8533 is also suitable for peer-to-peer applications such as switch fabrics and backplanes. Figure 3 represents a backplane where the device provides peer-to-peer data exchange for a large number of line cards where the CPU/Host plays the management role. Figure Dual Graphics Redundant Switch Fabric The PEX 8533 can be used in redundant switch fabrics for high availability applications. In the example shown in Figure 5, the PEX 8533 is used in conjunction with the PEX 8518 switch that offers non-transparent bridging NTB . The PEX 8533 provides high performance non-blocking switching while the PEX 8518s keep the two fabrics and hosts isolated. Figure Peer-to-Peer/Backplane Usage Graphics Fan-out Switch High resolution 3D graphics applications can take full advantage of the PEX 8533 three port configuration. Applications such as dual graphics, high resolution scientific use, and image processing can benefit from the performance of the PEX 8533 switch. Figure 4 illustrates use of the device in a dual graphics application while supporting PCI port expansion through another PLX PCIe switch. The upstream x16 port links to the Root Complex and the two downstream ports connect to the Graphics modules. The peer-to-peer support of the PEX 8533 allows the two GPU modules to communicate with each other for maximum performance. Figure 4 also illustrates use of PCIe bridges to connect to PCI and PCI-X busses. Figure Blade Server The number of ports and port widths can be configured as needed. This example assumes a x8 link to each CPU blade and a x8 link to each I/O blade. PLX Confidential Product Ordering Information Part Number PEX8533-AA25BI PEX8533-AA25BI G PEX 8533-AA RDK Description 32-Lane, 6-Port PCIe Switch, I-Temp, 35x35mm2 32-Lane, 6-Port PCIe Switch, Pb-Free, I-Temp, 35x35mm2 PEX 8533 Rapid Development Kit w/ x16 Connector Please visit the PLX Web site at or contact PLX sales at 408-774-9060 for sampling. 2008 PLX Technology, Inc. All rights reserved. PLX and the PLX logo are registered trademarks of PLX Technology, Inc. ExpressLane is a trademark of PLX Technology, Inc., which may be registered in some jurisdiction. All other product names that appear in this material are for identification purposes only and are acknowledged to be trademarks or registered trademarks of their respective companies. Information supplied by PLX is believed to be accurate and reliable, but PLX Technology, Inc. assumes no responsibility for any errors that may appear in this material. PLX Technology, Inc. reserves the right, without notice, to make changes in product design or specification. PEX8533-SIL-PB-P1-1.5 PLX Confidential 05/08

PDF Datasheet Preview

Version 2008

PEX 8533 General Features
o 32-lane PCI Express switch - Integrated SerDes
o Up to six configurable ports o 35mm x 35mm,
680-ball PBGA package o Pin Compatible with PEX 8532 o Typical Power Watts

PEX 8533 Key Features
o Standards Compliant - PCI Express Base Specification, r1.1 - PCI SHPC Specification, r1.0
o High Performance - Cut-through with 120ns packet latency - Max Payload Size of 1024 Bytes - Non-blocking switch fabric - Full line rate on all ports
o PCI Express Power Management - Link power management states L0, L0s, L1, L2/L3 Ready, and L3 - Device states D0 and D3hot
o Quality of Service QoS - Eight Traffic Classes per port - Round robin and weighted RR port arbitration
o Reliability, Availability, Serviceability - 3 Standard Hot-Plug Controllers - Upstream port as hot-plug client - Transaction Layer end-to-end CRC - Poison bit - INTA & FATAL ERROR signal support - Advanced Error Reporting in addition to PCIe baseline error reporting - Port Status bits and GPO available - Per port performance monitoring
• Average packet size, number of packets, CRC errors - JTAG boundary scan

PEX 8533

Flexible & Versatile PCI Express Switch

Multi-Purpose, Feature Rich PCI Express ExpressLane Switch

Highly Flexible Port Configurations The ExpressLaneTM PEX 8533 offers highly configurable ports. There are a maximum of 6 ports that can be configured to any legal width from x1 to x16, in any combination to support your specific bandwidth needs. The ports can be symmetric each port having the same lane width or asymmetric ports having different lane widths . Any of the ports can be designated as the upstream port, which can be changed dynamically.

High Performance The ExpressLaneTM PEX 8533 architecture supports packet cut-through with a latency of 115ns x8 to x8 . This, combined with large packet memory 256 to 1024 byte maximum payload size and non-blocking internal switch architecture, provide full line rate on its ports for performance hungry applications such as storage servers or storage switch fabrics.

End-to-End Packet Integrity The ExpressLaneTM PEX 8533 provides optional end-to-end CRC protection ECRC and Poison bit support to enable designs that require guaranteed error-free packets.

Configuration Flexibility The ExpressLaneTM PEX 8533 provides several ways to configure its operations. The device can be configured through strapping pins, I2C interface, CPU configuration cycles, or an optional serial EEPROM. This allows for easy debug during the development phase, performance monitoring during the operation phase, and driver or software upgrade.

Low Power with Granular SerDes Control The ExpressLaneTM PEX 8533 provides low power capability that is fully compliant with the PCI Express power management specification. In addition, the SerDes physical links can be turned off when unused for even lower power.

PLX Confidential

Flexible Port Width Configuration The lane width of each port can be individually configured through auto-negotiation, hardware strapping, host software configuration, I2C interface, or through an optional EEPROM.

The PEX 8533 supports a large number of port configurations. For example, if you are using the PEX 8533 in a fan-out application, you may configure the upstream port as a x8 and the downstream as one x8 port & four x4 ports two x8 & two x4 ports or other combinations, as long as you don’t run out of lanes 32 or ports For a dual-graphics application, you may configure the device as one x16 upstream and two x8 downstream ports see Figure The device can also support x2 & x1 ports by auto-negotiating its x4 ports to the width of the actual end-device it is interfacing with.
application where one or more of its downstream ports connect to PCI Express slots, the ports with the Hot Plug Controller feature can be used for these slots. The device will automatically manage the hot-plug event of its hotplug capable ports/slots. Furthermore, the hot-plug capable ports can be used as a hot-plug client or master, allowing it to be used on hot-pluggable carrier modules, backplanes, and fabric modules.

Fully Compliant Power Management For applications that require power management, the PEX 8533 device supports both link L0, L0s, L1, L2/L3 Ready, and L3 and device D0 and D3hot power management states, in compliance with the PCI Express power management specification.

SerDes Power and Signal Management The ExpressLane PEX 8533 supports software control of the SerDes outputs to allow optimization of power and signal strength in a system. The PLX SerDes implementation supports four levels of power off, low, typical and high. The SerDes block also supports loopback modes and advanced reporting of error conditions, which enables efficient debug and management of the entire system.

Figure Port Flexibility

Low Packet Latency The PEX 8533 supports packet cut-through with a latency of 115ns between symmetric x8 ingress and egress ports. The low latency enables many applications to achieve high throughput and performance. In addition to low latency, the device supports a packet payload size of up to 1024 bytes, enabling the user to achieve even higher throughput.

Hot Plug for High Availability Hot plug capability allows users to replace hardware modules and perform maintenance without powering down the system. The ExpressLane PEX 8533 hot plug capabilities and Advanced Error Reporting features make them suitable for high availability HA applications. Three of the six ports include a Standard Hot Plug Controller. If the PEX 8533 is used in an

Suitable for host-centric as well as peer-to-peer traffic patterns, the PEX 8533 can be configured for a wide variety of form factors and applications. Host Centric Fan-out The ExpressLane PEX 8533 device, with its versatile symmetric or asymmetric lane configuration capability, allows for user specific tuning to a variety of hostcentric applications.

Figure Fan-in/out Usage

PLX Confidential

Figure 2 shows a typical server-based design, where the Root Complex provides a PCI Express link that needs to be expanded into a larger number of smaller ports for a variety of I/O functions, each with different bandwidth requirements.

In this example, the ExpressLane PEX 8533 would typically have an 8-lane upstream port, and as many as 5 downstream ports. The downstream ports can be of differing widths if required.

Peer-to-Peer & Backplane Usage The PEX 8533 is also suitable for peer-to-peer applications such as switch fabrics and backplanes. Figure 3 represents a backplane where the device provides peer-to-peer data exchange for a large number of line cards where the CPU/Host plays the management role.

Figure Dual Graphics

Redundant Switch Fabric The PEX 8533 can be used in redundant switch fabrics for high availability applications. In the example shown in Figure 5, the PEX 8533 is used in conjunction with the PEX 8518 switch that offers non-transparent bridging NTB . The PEX 8533 provides high performance non-blocking switching while the PEX 8518s keep the two fabrics and hosts isolated.

Figure Peer-to-Peer/Backplane Usage

Graphics Fan-out Switch High resolution 3D graphics applications can take full advantage of the PEX 8533 three port configuration. Applications such as dual graphics, high resolution scientific use, and image processing can benefit from the performance of the PEX 8533 switch. Figure 4 illustrates use of the device in a dual graphics application while supporting PCI port expansion through another PLX PCIe switch. The upstream x16 port links to the Root Complex and the two downstream ports connect to the Graphics modules. The peer-to-peer support of the PEX 8533 allows the two GPU modules to communicate with each other for maximum performance. Figure 4 also illustrates use of PCIe bridges to connect to PCI and PCI-X busses.

Figure Blade Server

The number of ports and port widths can be configured as needed. This example assumes a x8 link to each CPU blade and a x8 link to each I/O blade.

PLX Confidential
Product Ordering Information

Part Number PEX8533-AA25BI PEX8533-AA25BI G PEX 8533-AA RDK

Description 32-Lane, 6-Port PCIe Switch, I-Temp, 35x35mm2 32-Lane, 6-Port PCIe Switch, Pb-Free, I-Temp, 35x35mm2

PEX 8533 Rapid Development Kit w/ x16 Connector

Please visit the PLX Web site at or contact PLX sales at 408-774-9060 for sampling.
2008 PLX Technology, Inc. All rights reserved. PLX and the PLX logo are registered trademarks of PLX Technology, Inc. ExpressLane is a trademark of PLX Technology, Inc., which may be registered in some jurisdiction. All other product names that appear in this material are for identification purposes only and are acknowledged to be trademarks or registered trademarks of their respective companies. Information supplied by PLX is believed to be accurate and reliable, but PLX Technology, Inc. assumes no responsibility for any errors that may appear in this material. PLX Technology, Inc. reserves the right, without notice, to make changes in product design or specification.

PEX8533-SIL-PB-P1-1.5

PLX Confidential
05/08

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Datasheet ID: PEX8533-AA25BI G 520505