HCTL-2017

HCTL-2017 Datasheet

HCTL-2017 and HCTL-2021 Quadrature Decoder/Counter Interface ICs

Part	Datasheet
HCTL-2017	HCTL-2017 (pdf)

PDF Datasheet Preview
HCTL-2017 and HCTL-2021 Quadrature Decoder/Counter Interface ICs Data Sheet The HCTL-2021/2017 is CMOS ICs that performs the quadrature decoder, counter, and bus interface function. The HCTL-2021/2017 is designed to improve system performance in digital closed loop motion control systems and digital data input systems. It does this by shifting time intensive quadrature decoder functions to a cost effective hardware solution. The HCTL-2021/2017 consists of a quadrature decoder logic, a binary up/down state counter, and an 8-bit bus interface. The use of Schmitt-triggered CMOS inputs and input noise filters allows reliable operation in noisy environments. The HCTL-2021/2017 contains 16-bit counter and provides TLL/CMOS compatible tri-state output buffers. Operation is specified for a temperature range from to +85°C at clock frequencies up to 33MHz. The HCTL-2021/2017 provides quadrature decoder output signals and cascade signals for use with many standard computer ICs. The HCTL-2021/2017 is compliant to RoHS directive and had been declared as a lead free product. • Interfaces Encoder to Microprocessor • 33 MHz Clock Operation • High Noise Immunity: Schmitt Trigger Inputs and Digital Noise Filter • 16-Bit Binary Up/Down Counter • Latched Outputs • 8-Bit Tristate Interface • 8 or 16-Bit Operating Modes • Quadrature Decoder Output Signals, Up/Down and Count • Cascade Output Signals, Up/Down and Count • Substantially Reduced System Software • 5V Operation VDD VSS • TTL/CMOS Compatible I/O • Operating Temperature -40°C to 85°C • 16-pin and 20-Pin Launch Pad Devices • Interface Quadrature Incremental Encoders to Microprocessors • Interface Digital Potentiometers to Digital Data Input Buses Part Number HCTL-2017 HCTL-2021 33 MHz clock operation. 16-bit counter. 33 MHz clock operation. 16-bit counter. Quadrature decoder output signals. Cascade output signals. Pinout A PINOUT B VDD 16 2 CLK D1 15 3 SEL D2 14 D3 13 5 RST D4 12 6 CH B D5 11 7 CH A D6 10 8 VSS PINOUT A VDD 20 2 CLK D1 19 3 SEL D2 18 D3 17 5 U/D CNTdec 16 6 NC CNTcas 15 7 RST D4 14 8 CH B D5 13 9 CH A

PDF Datasheet Preview

HCTL-2017 and HCTL-2021 Quadrature Decoder/Counter Interface ICs

Data Sheet

The HCTL-2021/2017 is CMOS ICs that performs the quadrature decoder, counter, and bus interface function. The HCTL-2021/2017 is designed to improve system performance in digital closed loop motion control systems and digital data input systems. It does this by shifting time intensive quadrature decoder functions to a cost effective hardware solution. The HCTL-2021/2017 consists of a quadrature decoder logic, a binary up/down state counter, and an 8-bit bus interface. The use of Schmitt-triggered CMOS inputs and input noise filters allows reliable operation in noisy environments. The HCTL-2021/2017 contains 16-bit counter and provides TLL/CMOS compatible tri-state output buffers. Operation is specified for a temperature range from to +85°C at clock frequencies up to 33MHz.

The HCTL-2021/2017 provides quadrature decoder output signals and cascade signals for use with many standard computer ICs.

The HCTL-2021/2017 is compliant to RoHS directive and had been declared as a lead free product.
• Interfaces Encoder to Microprocessor
• 33 MHz Clock Operation
• High Noise Immunity:

Schmitt Trigger Inputs and Digital Noise Filter
• 16-Bit Binary Up/Down Counter
• Latched Outputs
• 8-Bit Tristate Interface
• 8 or 16-Bit Operating Modes
• Quadrature Decoder Output Signals, Up/Down and

Count
• Cascade Output Signals, Up/Down and Count
• Substantially Reduced System Software
• 5V Operation VDD VSS
• TTL/CMOS Compatible I/O
• Operating Temperature -40°C to 85°C
• 16-pin and 20-Pin Launch Pad

Devices
• Interface Quadrature Incremental Encoders to Microprocessors
• Interface Digital Potentiometers to Digital Data Input Buses

Part Number HCTL-2017 HCTL-2021
33 MHz clock operation. 16-bit counter. 33 MHz clock operation. 16-bit counter. Quadrature decoder output signals. Cascade output signals.

Pinout A PINOUT B

VDD 16
2 CLK

D1 15
3 SEL

D2 14

D3 13
5 RST

D4 12
6 CH B

D5 11
7 CH A

D6 10
8 VSS

PINOUT A

VDD 20
2 CLK

D1 19
3 SEL

D2 18

D3 17
5 U/D CNTdec 16
6 NC CNTcas 15
7 RST

D4 14
8 CH B

D5 13
9 CH A

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived HCTL-2017 Datasheet file may be downloaded here without warranties.

Datasheet ID: HCTL-2017 520257