AFBR-79Q4Z

AFBR-79Q4Z Datasheet

AFBR-79Q4Z, AFBR-79Q4Z-D InfiniBand 4x QDR QSFP Pluggable, Parallel Fiber-Optics Module

Part	Datasheet
AFBR-79Q4Z	AFBR-79Q4Z (pdf)

Related Parts	Information
AFBR-79Q4Z-D	AFBR-79Q4Z-D

PDF Datasheet Preview
AFBR-79Q4Z, AFBR-79Q4Z-D InfiniBand 4x QDR QSFP Pluggable, Parallel Fiber-Optics Module Data Sheet The Avago Technologies AFBR-79Q4Z is a Four-Channel, Pluggable, Parallel, Fiber-Optic QSFP Transceiver for QDR InfiniBand and proprietary applications. This transceiver is a high performance module for short-range multi-lane data communication and interconnect applications. It integrates four data lanes in each direction with 40 Gbps aggregate bandwidth. Each lane can operate at 10 Gbps up to 100 m using OM3 fiber. These modules are designed to operate over multimode fiber systems using a nominal wavelength of 850nm. The electrical interface uses a 38-contact edge type connector. The optical interface uses an 8 or 12 fiber MPO connector. This module incor- porates Avago Technologies proven integrated circuit and VCSEL technology to provide reliable long life, high performance, and consistent service. • InfiniBand QDR 4 x 10G , DDR 4 x 5G and SDR 4 x 2.5G interconnects • High Performance and High Productivity computer interconnects • Data Aggregation, Backplane and Proprietary Density Applications • PCI-Express, SAS/SATA, Fibre Channel compatible interconnect • Datacom and Telecom switch and router backplane connections • Compliant to the InfiniBand Architecture Release QDR Specification • High Channel Capacity up to 40 Gbps per module, bi-directional operation • Operates up to 10 Gbps with 8b/10b compatible coded data • Backwards compatible to 5Gbps DDR IB and Gbps SDR IB • 0 to 70°C case temperature operating range • Proven High Reliability 850 nm technology Avago Technologies VCSEL array transmitter and Avago Technologies PIN array receiver • High port density 21mm horizontal port pitch • Up to 100m links at 10G/channel using OM3 multimode fiber • Four independent transmitter channels and 4 independent receiver channels per module • Two Wire Serial TWS interface with maskable interrupt for expanded functionality including: Individual channel functions disable, squelch disable A/D readback module temperature and supply voltages, per channel laser current and laser power, or received power Status per channel Tx fault, electrical transmitter or optical receiver LOS, and alarm flags Patent - Part Number Ordering Options QDR 10G InfiniBand QDR 10G InfiniBand With Full Digital Diagnostic Monitoring Evaluation Board Evaluation Kit * Includes GUI and User Guide ** Includes GUI, User Guide, i-Port and Power Supply AFBR-79Q4Z AFBR-79Q4Z-D AFBR-79Q4EKZ* AFBR-79Q2EKZ** 1x4 VCSEL Array Optical Interface Electrical Interface Din[3:0][p/n] 8 SCL SDA Mod Sel LPMode ModPresL ResetL IntL Dout[3:0][p/n] 8 TX Input 4 Channels Control RX Output 4 Channels Laser Driver 4 Channels Diagnostic Monitors TIA 4 Channels 1x4 PIN Array Figure Transceiver Block Diagram Transmitter The optical transmitter portion of the transceiver see Figure 1 incorporates a 4-channel VCSEL Vertical Cavity Surface Emitting Laser array, a 4-channel input buffer and laser driver, diagnostic monitors, and control and bias blocks. The transmitter is designed for IEC-60825 and CDRH eye safety compliance Class 1M out of the module. The Tx Input Buffer provides CML compatible differential inputs presenting a nominal differential input impedance of 100 Ohms. AC coupling capacitors are located inside the QSFP module and are not required on the host board. For module control and interrogation, the control interface LVTTL compatible incorporates a Two Wire Serial TWS interface of clock and data signals. Modules with Full Digital Diagnostic Monitoring have monitors for VCSEL bias, light output LOP , temperature, and power supply voltage implemented results are available through the TWS interface. Alarm thresholds are established for the monitored attributes. Flags are set and interrupts generated when the attributes are outside the thresholds. Flags are also set and interrupts generated for loss of input signal LOS and transmitter fault conditions. All flags are latched and will remain set even if the condition initiating the latch clears and operation resumes. All interrupts can be masked and flags are reset by reading the appropriate flag register. The optical output will squelch for loss of input signal unless squelch is disabled. Fault detection or channel deactivation through the TWS interface will disable the channel. Status, alarm and fault information are available via the TWS interface. To reduce the need for polling, the hardware interrupt signal is provided to inform hosts of an assertion of an alarm, LOS and/or Tx fault. Receiver The optical receiver portion of the transceiver see Figure 1 incorporates a 4-channel PIN photodiode array, a 4-channel TIA array, a 4 channel output buffer, diagnostic monitors, and control and bias blocks. The Rx Output Buffer provides CML compatible differential outputs for the high speed electrical interface presenting nominal single-ended output impedances of 50 Ohms to AC ground and 100 Ohms differentially that should be differentially terminated with 100 Ohms. AC coupling capacitors are located inside the QSFP module and are not required on the host board. Modules with Full Digital Diagnostic Monitoring have a monitor for optical input power results are available through the TWS interface. Alarm thresholds are established for the monitored attributes. Flags are set and interrupts generated when the attributes are outside the thresholds. Flags are also set and interrupts generated for loss of optical input signal LOS . All flags are latched and will remain set even if the condition initiating the latch clears and operation resumes. All interrupts can be masked and flags are reset upon reading the appropriate flag register. The electrical output will squelch for loss of input signal unless squelch is disabled and channel de-activation through TWS interface. Status and alarm information are available via the TWS interface. To reduce the need for polling, the hardware interrupt signal is provided to inform hosts of an assertion of an alarm and/or LOS. High Speed Signal Interface Figure 2 shows the interface between an ASIC/SerDes and the QSFP module. For simplicity, only one channel is shown. As shown in Figure 2, the compliance points are on the host board side of the electrical connectors. Unused inputs and outputs should be terminated with 100 differential loads. QSFP compliance and reference points are as follows: A Host ASIC transmitter output at ASIC package contact on a DUT board Reference point. B Host ASIC transmitter output across the Host Board and Host Edge Card connector at the Module Card Edge interface Reference point. B’ Host ASIC transmitter output across the Host Board at Host Edge Card Connector Compliance point. C QSFP receiver output at the Module Card Edge Interface Reference point. C’ QSFP receiver output at Host Edge Card Connector Compliance point. D QSFP receiver output at Host ASIC package receiver input contact on a DUT board Reference point. Host Board Only one channel shown for simplicity Rx Out p Rx Out n Rx

PDF Datasheet Preview

AFBR-79Q4Z, AFBR-79Q4Z-D InfiniBand 4x QDR QSFP Pluggable, Parallel Fiber-Optics Module

Data Sheet

The Avago Technologies AFBR-79Q4Z is a Four-Channel, Pluggable, Parallel, Fiber-Optic QSFP Transceiver for QDR InfiniBand and proprietary applications. This transceiver is a high performance module for short-range multi-lane data communication and interconnect applications. It integrates four data lanes in each direction with 40 Gbps aggregate bandwidth. Each lane can operate at 10 Gbps up to 100 m using OM3 fiber. These modules are designed to operate over multimode fiber systems using a nominal wavelength of 850nm. The electrical interface uses a 38-contact edge type connector. The optical interface uses
an 8 or 12 fiber MPO connector. This module incor-
porates Avago Technologies proven integrated circuit and VCSEL technology to provide reliable long life, high performance, and consistent service.
• InfiniBand QDR 4 x 10G , DDR 4 x 5G and SDR 4 x 2.5G interconnects
• High Performance and High Productivity computer interconnects
• Data Aggregation, Backplane and Proprietary Density Applications
• PCI-Express, SAS/SATA, Fibre Channel compatible interconnect
• Datacom and Telecom switch and router backplane connections
• Compliant to the InfiniBand Architecture Release QDR Specification
• High Channel Capacity up to 40 Gbps per module, bi-directional operation
• Operates up to 10 Gbps with 8b/10b compatible coded data
• Backwards compatible to 5Gbps DDR IB and Gbps SDR IB
• 0 to 70°C case temperature operating range
• Proven High Reliability 850 nm technology Avago Technologies VCSEL array transmitter and Avago Technologies PIN array receiver
• High port density 21mm horizontal port pitch
• Up to 100m links at 10G/channel using OM3 multimode fiber
• Four independent transmitter channels and 4 independent receiver channels per module
• Two Wire Serial TWS interface with maskable interrupt for expanded functionality including:

Individual channel functions disable, squelch disable

A/D readback module temperature and supply voltages, per channel laser current and laser power, or received power

Status per channel Tx fault, electrical transmitter or optical receiver LOS, and alarm flags

Patent -
Part Number Ordering Options

QDR 10G InfiniBand QDR 10G InfiniBand With Full Digital Diagnostic Monitoring

Evaluation Board Evaluation Kit * Includes GUI and User Guide ** Includes GUI, User Guide, i-Port and Power Supply

AFBR-79Q4Z AFBR-79Q4Z-D

AFBR-79Q4EKZ* AFBR-79Q2EKZ**
1x4 VCSEL Array

Optical Interface

Electrical Interface

Din[3:0][p/n] 8

SCL SDA Mod Sel LPMode ModPresL ResetL IntL

Dout[3:0][p/n] 8

TX Input 4 Channels

Control

RX Output 4 Channels

Laser Driver 4 Channels

Diagnostic Monitors

TIA 4 Channels
1x4 PIN Array

Figure Transceiver Block Diagram

Transmitter

The optical transmitter portion of the transceiver see Figure 1 incorporates a 4-channel VCSEL Vertical Cavity Surface Emitting Laser array, a 4-channel input buffer and laser driver, diagnostic monitors, and control and bias blocks. The transmitter is designed for IEC-60825 and CDRH eye safety compliance Class 1M out of the module. The Tx Input Buffer provides CML compatible differential inputs presenting a nominal differential input impedance of 100 Ohms. AC coupling capacitors are located inside the QSFP module and are not required on the host board. For module control and interrogation, the control interface LVTTL compatible incorporates a Two Wire Serial TWS interface of clock and data signals.

Modules with Full Digital Diagnostic Monitoring have monitors for VCSEL bias, light output LOP , temperature, and power supply voltage implemented results are available
through the TWS interface. Alarm thresholds are established for the monitored attributes. Flags are set and interrupts generated when the attributes are outside the thresholds. Flags are also set and interrupts generated for loss of input signal LOS and transmitter fault conditions. All flags are latched and will remain set even if the condition initiating the latch clears and operation resumes. All interrupts can be masked and flags are reset by reading the appropriate flag register.

The optical output will squelch for loss of input signal unless squelch is disabled. Fault detection or channel deactivation through the TWS interface will disable the channel. Status, alarm and fault information are available via the TWS interface. To reduce the need for polling, the hardware interrupt signal is provided to inform hosts of an assertion of an alarm, LOS and/or Tx fault.

Receiver

The optical receiver portion of the transceiver see Figure 1 incorporates a 4-channel PIN photodiode array, a 4-channel TIA array, a 4 channel output buffer, diagnostic monitors, and control and bias blocks. The Rx Output Buffer provides CML compatible differential outputs for the high speed electrical interface presenting nominal single-ended output impedances of 50 Ohms to AC ground and 100 Ohms differentially that should be differentially terminated with 100 Ohms. AC coupling capacitors are located inside the QSFP module and are not required on the host board.

Modules with Full Digital Diagnostic Monitoring have a monitor for optical input power results are available through the TWS interface. Alarm thresholds are established for the monitored attributes. Flags are set and interrupts generated when the attributes are outside the thresholds.

Flags are also set and interrupts generated for loss of optical input signal LOS . All flags are latched and will remain set even if the condition initiating the latch clears and operation resumes. All interrupts can be masked and flags are reset upon reading the appropriate flag register.

The electrical output will squelch for loss of input signal unless squelch is disabled and channel de-activation through TWS interface. Status and alarm information are available via the TWS interface. To reduce the need for polling, the hardware interrupt signal is provided to inform hosts of an assertion of an alarm and/or LOS.

High Speed Signal Interface

Figure 2 shows the interface between an ASIC/SerDes and the QSFP module. For simplicity, only one channel is shown. As shown in Figure 2, the compliance points are on the host board side of the electrical connectors. Unused inputs and outputs should be terminated with 100 differential loads.

QSFP compliance and reference points are as follows:

A Host ASIC transmitter output at ASIC package contact on a DUT board Reference point.

B Host ASIC transmitter output across the Host Board and Host Edge Card connector at the Module Card Edge interface Reference point.

B’ Host ASIC transmitter output across the Host Board at Host Edge Card Connector Compliance point.

C QSFP receiver output at the Module Card Edge Interface Reference point.

C’ QSFP receiver output at Host Edge Card Connector Compliance point.

D QSFP receiver output at Host ASIC package receiver input contact on a DUT board Reference point.

Host Board Only one channel shown for simplicity

Rx Out p

Rx Out n Rx

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Datasheet ID: AFBR-79Q4Z 520056