ADN2811ACPZ-CML-RL

ADN2811ACPZ-CML-RL Datasheet

OC-48/OC-48 FEC Clock and Data Recovery ADN2811

Part	Datasheet
ADN2811ACPZ-CML-RL	ADN2811ACPZ-CML-RL (pdf)

PDF Datasheet Preview
Data Sheet OC-48/OC-48 FEC Clock and Data Recovery ADN2811 PRODUCT DESCRIPTION Meets SONET requirements for jitter transfer/generation/ tolerance Quantizer sensitivity 4 mV typical Adjustable slice level ±100 mV GHz minimum bandwidth Patented clock recovery architecture Loss of signal detect range 3 mV to 15 mV Single reference clock frequency for both native SONET and 15/14 7% wrapper rate Choice of MHz, MHz, MHz, or MHz REFCLK LVPECL/LVDS/LVCMOS/LVTTL compatible inputs LVPECL/LVDS only at MHz on-chip oscillator to be used with external crystal Loss of lock indicator Loopback mode for high speed test data Output squelch and bypass features Single-supply operation V Low power 540 mW typical 7 mm x 7 mm, 48-lead LFCSP SONET OC-48, SDH STM-16, and 15/14 FEC WDM transponders Regenerators/repeaters Test equipment Backplane applications The ADN2811 provides the receiver functions of quantization, signal level detect, and clock and data recovery at OC-48 and OC-48 FEC rates. All SONET jitter requirements are met, including jitter transfer, jitter generation, and jitter tolerance. All specifications are quoted for −40°C to +85°C ambient temperature, unless otherwise noted. The device is intended for WDM system applications and can be used with either an external reference clock or an on-chip oscillator with external crystal. Both the Gbps and Gbps digital wrapper rates are supported by the ADN2811, without any change of reference clock. This device, together with a PIN diode and a TIA preamplifier, can implement a highly integrated, low cost, low power, fiber optic receiver. The receiver front end signal detect circuit indicates when the input signal level has fallen below a user-adjustable threshold. The signal detect circuit has hysteresis to prevent chatter at the output. The ADN2811 is available in a compact, 7 mm x 7 mm, 48-lead chip scale package. FUNCTIONAL BLOCK DIAGRAM SLICEP/N VCC VEE ADN2811 QUANTIZER NIN PHASE SHIFTER PHASE DET. LOOP FILTER VREF LEVEL DETECT THRADJ SDOUT DATA RETIMING DATAOUTP/N 2 CLKOUTP/N LOOP FILTER FREQUENCY LOCK DETECTOR FRACTIONAL DIVIDER XTAL OSC REFSEL[0..1] REFCLKP/N XO1 REFSEL RATE 03019-B-001 Figure Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other Data Sheet Functional Description 12 Clock and Data 12 Limiting Amplifier 12 Slice Adjust 12 Loss of Signal LOS Detector 12 Reference Clock 12 Lock Detector Operation 13 Squelch Mode 14 Test Modes Bypass and 14 Applications Information 15 PCB Design Guidelines 15 Choosing AC-Coupling Capacitors 17 DC-Coupled Application 18 LOL Toggling during Loss of Input Data 18 Outline Dimensions 19 Ordering Guide 19 Data Sheet ADN2811 SPECIFICATIONS Table TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V, CF = µF, SLICEP = SLICEN = VCC, unless otherwise noted Parameter Test Conditions/Comments Typ Max CHARACTERISTICS Input Voltage Range At PIN or NIN, dc-coupled Peak-to-Peak Differential Input Input Common-Mode Level DC-coupled. See Figure 24 Differential Input Sensitivity ac-coupled1, BER = 1 x 10−10 Input Overdrive Figure 6 Input Offset Input rms Noise BER = 1 x 10−10 CHARACTERISTICS Upper dB Bandwidth Small Signal Gain Differential At GHz −15 Input Resistance Differential Input Capacitance Pulse Width Distortion2 QUANTIZER SLICE ADJUSTMENT Gain SliceP − SliceN = V Control Voltage Range SliceP − SliceN At SliceP or SliceN Slice Threshold Offset LEVEL SIGNAL DETECT SDOUT Level Detect Range See Figure 4 RTHRESH = 2 ORDERING GUIDE Model1 ADN2811ACPZ-CML ADN2811ACPZ-CML-RL EVAL-ADN2811-CML COMPLIANT TO JEDEC STANDARDS MO-220-WKKD. Figure 48-Lead Frame Chip Scale Package [LFCSP] 7 mm x 7 mm Body and mm Package Height CP-48-4 Dimensions shown in millimeters Temperature Range −40°C to +85°C −40°C to +85°C Package Description 48-Lead Frame Chip Scale Package [LFCSP] 48-Lead Frame Chip Scale Package, Tape-Reel, 2500 pcs [LFCSP] Evaluation Board 1 Z = RoHS Compliant Part. Package Option CP-48-4 CP-48-4 ADN2811 NOTES Data Sheet Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03019-0-5/16 C

PDF Datasheet Preview

Data Sheet

OC-48/OC-48 FEC Clock and Data Recovery ADN2811

PRODUCT DESCRIPTION

Meets SONET requirements for jitter transfer/generation/ tolerance

Quantizer sensitivity 4 mV typical Adjustable slice level ±100 mV GHz minimum bandwidth Patented clock recovery architecture Loss of signal detect range 3 mV to 15 mV Single reference clock frequency for both native SONET and
15/14 7% wrapper rate Choice of MHz, MHz, MHz, or MHz

REFCLK LVPECL/LVDS/LVCMOS/LVTTL compatible inputs

LVPECL/LVDS only at MHz on-chip oscillator to be used with external crystal Loss of lock indicator Loopback mode for high speed test data Output squelch and bypass features Single-supply operation V Low power 540 mW typical 7 mm x 7 mm, 48-lead LFCSP

SONET OC-48, SDH STM-16, and 15/14 FEC WDM transponders Regenerators/repeaters Test equipment Backplane applications

The ADN2811 provides the receiver functions of quantization, signal level detect, and clock and data recovery at OC-48 and OC-48 FEC rates. All SONET jitter requirements are met, including jitter transfer, jitter generation, and jitter tolerance. All specifications are quoted for −40°C to +85°C ambient temperature, unless otherwise noted.

The device is intended for WDM system applications and can be used with either an external reference clock or an on-chip oscillator with external crystal. Both the Gbps and Gbps digital wrapper rates are supported by the ADN2811, without any change of reference clock.

This device, together with a PIN diode and a TIA preamplifier, can implement a highly integrated, low cost, low power, fiber optic receiver.

The receiver front end signal detect circuit indicates when the input signal level has fallen below a user-adjustable threshold. The signal detect circuit has hysteresis to prevent chatter at the output.

The ADN2811 is available in a compact, 7 mm x 7 mm, 48-lead chip scale package.

FUNCTIONAL BLOCK DIAGRAM

SLICEP/N

VCC VEE

ADN2811

QUANTIZER NIN

PHASE SHIFTER

PHASE DET.

LOOP FILTER

VREF

LEVEL DETECT

THRADJ SDOUT

DATA RETIMING

DATAOUTP/N
2 CLKOUTP/N

LOOP FILTER

FREQUENCY LOCK

DETECTOR

FRACTIONAL DIVIDER

XTAL OSC

REFSEL[0..1] REFCLKP/N XO1

REFSEL

RATE
03019-B-001

Figure

Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
Data Sheet

Functional Description 12 Clock and Data 12 Limiting Amplifier 12 Slice Adjust 12 Loss of Signal LOS Detector 12 Reference Clock 12 Lock Detector Operation 13 Squelch Mode 14 Test Modes Bypass and 14

Applications Information 15 PCB Design Guidelines 15 Choosing AC-Coupling Capacitors 17 DC-Coupled Application 18 LOL Toggling during Loss of Input Data 18
Outline Dimensions 19 Ordering Guide 19

Data Sheet

ADN2811

SPECIFICATIONS

Table TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V, CF = µF, SLICEP = SLICEN = VCC, unless otherwise noted

Parameter

Test Conditions/Comments

Typ Max

CHARACTERISTICS

Input Voltage Range

At PIN or NIN, dc-coupled

Peak-to-Peak Differential Input

Input Common-Mode Level

DC-coupled. See Figure 24

Differential Input Sensitivity
ac-coupled1, BER = 1 x 10−10

Input Overdrive

Figure 6

Input Offset

Input rms Noise

BER = 1 x 10−10

CHARACTERISTICS

Upper dB Bandwidth

Small Signal Gain

Differential

At GHz
−15

Input Resistance

Differential

Input Capacitance

Pulse Width Distortion2

QUANTIZER SLICE ADJUSTMENT

Gain

SliceP − SliceN = V

Control Voltage Range

SliceP − SliceN

At SliceP or SliceN

Slice Threshold Offset

LEVEL SIGNAL DETECT SDOUT

Level Detect Range See Figure 4

RTHRESH = 2
ORDERING GUIDE

Model1 ADN2811ACPZ-CML ADN2811ACPZ-CML-RL EVAL-ADN2811-CML

COMPLIANT TO JEDEC STANDARDS MO-220-WKKD.

Figure 48-Lead Frame Chip Scale Package [LFCSP] 7 mm x 7 mm Body and mm Package Height CP-48-4 Dimensions shown in millimeters

Temperature Range −40°C to +85°C −40°C to +85°C

Package Description 48-Lead Frame Chip Scale Package [LFCSP] 48-Lead Frame Chip Scale Package, Tape-Reel, 2500 pcs [LFCSP] Evaluation Board
1 Z = RoHS Compliant Part.

Package Option CP-48-4 CP-48-4

ADN2811 NOTES

Data Sheet

Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.

D03019-0-5/16 C

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived ADN2811ACPZ-CML-RL Datasheet file may be downloaded here without warranties.

Datasheet ID: ADN2811ACPZ-CML-RL 517844