ADM690AQ

ADM690AQ Datasheet

The ADM690, ADM692 and ADM694 are available in 8-pin DIP packages and provide:

Part	Datasheet
ADM690AQ	ADM690AQ (pdf)

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Microprocessor Supervisory Circuits FEATURES Superior Upgrade for Specified Over Temperature Low Power Consumption 5 mW Precision Voltage Monitor Reset Assertion Down to 1 V VCC Low Switch On-Resistance Normal, 20 in Backup High Current Drive 100 mA Watchdog ms, s, or Adjustable 600 nA Standby Current Automatic Battery Backup Power Switching Extremely Fast Gating of Chip Enable Signals 5 ns Voltage Monitor for Power Fail APPLICATIONS Microprocessor Systems Computers Controllers Intelligent Instruments Automotive Systems GENERAL DESCRIPTION The family of supervisory circuits offers complete single chip solutions for power supply monitoring and battery control functions in microprocessor systems. These functions include µP reset, backup battery switchover, watchdog timer, CMOS RAM write protection, and power failure warning. The complete family provides a variety of configurations to satisfy most microprocessor system requirements. The ADM690, ADM692 and ADM694 are available in 8-pin DIP packages and provide: Power-on reset output during power-up, power-down and brownout conditions. The RESET output remains operational with VCC as low as 1 V. Battery backup switching for CMOS RAM, CMOS microprocessor or other low power logic. A reset pulse if the optional watchdog timer has not been toggled within a specified time. A V threshold detector for power fail warning, low battery detection, or to monitor a power supply other than +5 V. The ADM691, ADM693 and ADM695 are available in 16-pin DIP and small outline packages and provide three additional functions. Write protection of CMOS RAM or EEPROM. Adjustable reset and watchdog timeout periods. Separate watchdog timeout, backup battery switchover, and low VCC status outputs. FUNCTIONAL BLOCK DIAGRAMS VBATT VOUT 4.65V 1 RESET GENERATOR2 RESET WATCHDOG INPUT WDI POWER FAIL INPUT PFI WATCHDOG TRANSITION DETECTOR 1.6s 1.3V ADM690 ADM692 ADM694 POWER FAIL OUTPUT PFO 1VOLTAGE DETECTOR = 4.65V ADM690, ADM694 4.40V ADM692 2RESET PULSE WIDTH = 50ms ADM690, ADM692 200ms ADM694 BATT ON VBATT VCC CEIN 4.65V 1 OSC IN OSC SEL RESET & WATCHDOG TIMEBASE ADM691 ADM693 ADM695 VOUT CEOUT LOW LINE RESET GENERATOR RESET WATCHDOG INPUT WDI POWER FAIL INPUT PFI ORDERING GUIDE Temperature Range to +85°C to +85°C to +125°C to +85°C to +85°C to +85°C to +125°C to +85°C to +85°C to +125°C to +85°C to +85°C to +85°C to +125°C to +85°C to +85°C to +125°C to +85°C to +85°C to +85°C to +125°C Package Option N-8 Q-8 Q-8 N-16 R-16 Q-16 Q-16 N-8 Q-8 Q-8 N-16 R-16 Q-16 Q-16 N-8 Q-8 Q-8 N-16 R-16 Q-16 Q-16 *Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods of time may affect device reliability. CAUTION ESD electrostatic discharge sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE PIN FUNCTION DESCRIPTION Mnemonic Function VCC VBATT VOUT GND RESET WDI PFI PFO CEIN CEOUT BATT ON LOW LINE RESET OSC SEL OSC IN Power Supply Input +5 V Nominal. Backup Battery Input. Connect to Ground if a backup battery is not used. Output Voltage, VCC or VBATT is internally switched to VOUT depending on which is at the highest potential. VOUT can supply up to 100 mA to power CMOS RAM. Connect VOUT to VCC if VOUT and VBATT are not used. 0 V. Ground reference for all signals. Logic Output. RESET goes low if VCC falls below the Reset Threshold VCC falls below VBATT The watchdog timer is not serviced within its timeout period. The reset threshold is typically V for the ADM690/ADM691/ADM694/ADM695 and V for the ADM692 and ADM693. RESET remains low for 50 ms ADM690/ADM691/ADM692/ADM693 or 200 ms ADM694/ADM695 after VCC returns above the threshold. RESET also goes low for 50 200 ms if the watchdog timer is enabled but not serviced within its timeout period. The RESET pulse width can be adjusted on the ADM691/ADM693/ADM695 as shown in Table I. The RESET output has an internal 3 µA pull up, and can either connect to an open collector Reset bus or directly drive a CMOS gate without an external pull-up resistor. Watchdog Input. WDI is a three level input. If WDI remains either high or low for longer than the watchdog timeout period, RESET pulses low and WDO goes low. The timer resets with each transition on the WDI line. The watchdog timer may be disabled if WDI is left floating or is driven to midsupply. Power Fail Input. PFI is the noninverting input to the Power Fail Comparator when PFI is less than V, PFO goes low. Connect PFI to GND or VOUT when not used. Power Fail Output. PFO is the output of the Power Fail Comparator. It goes low when PFI is less than V. The comparator is turned off and PFO goes low when VCC is below VBATT. Logic Input. The input to the CE gating circuit. Connect to GND or VOUT if not used. Logic Output. CEOUT is a gated version of the CEIN signal. CEOUT tracks CEIN when VCC is above the reset threshold. If VCC is below the reset threshold, CEOUT is forced high. See Figures 5 and Logic Output. BATT ON goes high when VOUT is internally switched to the VBATT input. It goes low when VOUT is internally switched to VCC. The output typically sinks 35 mA and can directly drive the base of an external PNP transistor to increase the output current above the 100 mA rating of VOUT. Logic Output. LOW LINE goes low when VCC falls below the reset threshold. It returns high as soon as VCC rises above the reset threshold. Logic Output. RESET is an active high output. It is the inverse of RESET. Logic Oscillator Select Input. When OSC SEL is unconnected floating or driven high, the internal oscillator sets the reset active time and watchdog timeout period. When OSC SEL is low, the external oscillator input, OSC IN, is enabled. OSC SEL has a 3 µA internal pull up, see Table I . Oscillator Logic Input. With OSC SEL low, OSC IN can be driven by an external clock signal or an external capacitor can be connected between OSC IN and GND. This sets both the reset active pulse timing and the watchdog timeout period see Table I and Figure With OSC SEL high or floating, the internal oscillator is enabled and the reset active time is fixed at 50 ms typ. ADM691/ADM693 or 200 ms typ ADM695 . In this mode the OSC IN pin selects between fast 100 ms and slow s watchdog timeout periods. In both modes, the timeout period immediately after a reset is s typical. Logic Output. The Watchdog Output, WDO, goes low if WDI remains either high or low for longer than the watchdog timeout period. WDO is set high by the next transition at WDI. If WDI is unconnected or at midsupply, the watchdog timer is disabled and WDO remains high. WDO also goes high when LOW LINE goes low. PIN CONFIGURATIONS

PDF Datasheet Preview

Microprocessor Supervisory Circuits

FEATURES Superior Upgrade for Specified Over Temperature Low Power Consumption 5 mW Precision Voltage Monitor Reset Assertion Down to 1 V VCC Low Switch On-Resistance Normal,
20 in Backup High Current Drive 100 mA Watchdog ms, s, or Adjustable 600 nA Standby Current Automatic Battery Backup Power Switching Extremely Fast Gating of Chip Enable Signals 5 ns Voltage Monitor for Power Fail

APPLICATIONS Microprocessor Systems Computers Controllers Intelligent Instruments Automotive Systems

GENERAL DESCRIPTION The family of supervisory circuits offers complete single chip solutions for power supply monitoring and battery control functions in microprocessor systems. These functions include µP reset, backup battery switchover, watchdog timer, CMOS RAM write protection, and power failure warning. The complete family provides a variety of configurations to satisfy most microprocessor system requirements.

The ADM690, ADM692 and ADM694 are available in 8-pin DIP packages and provide:

Power-on reset output during power-up, power-down and brownout conditions. The RESET output remains operational with VCC as low as 1 V.

Battery backup switching for CMOS RAM, CMOS microprocessor or other low power logic.

A reset pulse if the optional watchdog timer has not been toggled within a specified time.

A V threshold detector for power fail warning, low battery detection, or to monitor a power supply other than +5 V.

The ADM691, ADM693 and ADM695 are available in 16-pin DIP and small outline packages and provide three additional functions.

Write protection of CMOS RAM or EEPROM.

Adjustable reset and watchdog timeout periods.

Separate watchdog timeout, backup battery switchover, and low VCC status outputs.

FUNCTIONAL BLOCK DIAGRAMS

VBATT VOUT
4.65V 1

RESET GENERATOR2

RESET

WATCHDOG INPUT WDI

POWER FAIL INPUT PFI

WATCHDOG TRANSITION DETECTOR
1.6s
1.3V

ADM690 ADM692 ADM694

POWER FAIL OUTPUT PFO
1VOLTAGE DETECTOR = 4.65V ADM690, ADM694 4.40V ADM692
2RESET PULSE WIDTH = 50ms ADM690, ADM692 200ms ADM694

BATT ON

VBATT

VCC CEIN
4.65V 1

OSC IN OSC SEL

RESET & WATCHDOG TIMEBASE

ADM691 ADM693 ADM695

VOUT

CEOUT LOW LINE

RESET GENERATOR

RESET

WATCHDOG INPUT WDI

POWER FAIL INPUT PFI
ORDERING GUIDE

Temperature Range
to +85°C to +85°C to +125°C
to +85°C to +85°C to +85°C to +125°C
to +85°C to +85°C to +125°C
to +85°C to +85°C to +85°C to +125°C
to +85°C to +85°C to +125°C
to +85°C to +85°C to +85°C to +125°C

Package Option

N-8 Q-8 Q-8

N-16 R-16 Q-16 Q-16

N-8 Q-8 Q-8

N-16 R-16 Q-16 Q-16

N-8 Q-8 Q-8

N-16 R-16 Q-16 Q-16
*Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods of time may affect device reliability.

CAUTION ESD electrostatic discharge sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

PIN FUNCTION DESCRIPTION

Mnemonic Function

VCC VBATT VOUT GND RESET

WDI PFI PFO CEIN CEOUT BATT ON LOW LINE RESET OSC SEL OSC IN

Power Supply Input +5 V Nominal.

Backup Battery Input. Connect to Ground if a backup battery is not used.

Output Voltage, VCC or VBATT is internally switched to VOUT depending on which is at the highest potential. VOUT can supply up to 100 mA to power CMOS RAM. Connect VOUT to VCC if VOUT and VBATT are not used.
0 V. Ground reference for all signals.

Logic Output. RESET goes low if VCC falls below the Reset Threshold VCC falls below VBATT The watchdog timer is not serviced within its timeout period.

The reset threshold is typically V for the ADM690/ADM691/ADM694/ADM695 and V for the ADM692 and ADM693. RESET remains low for 50 ms ADM690/ADM691/ADM692/ADM693 or 200 ms ADM694/ADM695 after VCC returns above the threshold. RESET also goes low for 50 200 ms if the watchdog timer is enabled but not serviced within its timeout period. The RESET pulse width can be adjusted on the ADM691/ADM693/ADM695 as shown in Table I. The RESET output has an internal 3 µA pull up, and can either connect to an open collector Reset bus or directly drive a CMOS gate without an external pull-up resistor.

Watchdog Input. WDI is a three level input. If WDI remains either high or low for longer than the watchdog timeout period, RESET pulses low and WDO goes low. The timer resets with each transition on the WDI line. The watchdog timer may be disabled if WDI is left floating or is driven to midsupply.

Power Fail Input. PFI is the noninverting input to the Power Fail Comparator when PFI is less than V, PFO goes low. Connect PFI to GND or VOUT when not used.

Power Fail Output. PFO is the output of the Power Fail Comparator. It goes low when PFI is less than V. The comparator is turned off and PFO goes low when VCC is below VBATT.

Logic Input. The input to the CE gating circuit. Connect to GND or VOUT if not used.

Logic Output. CEOUT is a gated version of the CEIN signal. CEOUT tracks CEIN when VCC is above the reset threshold. If VCC is below the reset threshold, CEOUT is forced high. See Figures 5 and

Logic Output. BATT ON goes high when VOUT is internally switched to the VBATT input. It goes low when VOUT is internally switched to VCC. The output typically sinks 35 mA and can directly drive the base of an external PNP transistor to increase the output current above the 100 mA rating of VOUT.

Logic Output. LOW LINE goes low when VCC falls below the reset threshold. It returns high as soon as VCC rises above the reset threshold.

Logic Output. RESET is an active high output. It is the inverse of RESET.

Logic Oscillator Select Input. When OSC SEL is unconnected floating or driven high, the internal oscillator sets the reset active time and watchdog timeout period. When OSC SEL is low, the external oscillator input, OSC IN, is enabled. OSC SEL has a 3 µA internal pull up, see Table I .

Oscillator Logic Input. With OSC SEL low, OSC IN can be driven by an external clock signal or an external capacitor can be connected between OSC IN and GND. This sets both the reset active pulse timing and the watchdog timeout period see Table I and Figure With OSC SEL high or floating, the internal oscillator is enabled and the reset active time is fixed at 50 ms typ. ADM691/ADM693 or 200 ms typ ADM695 . In this mode the OSC IN pin selects between fast 100 ms and slow s watchdog timeout periods. In both modes, the timeout period immediately after a reset is s typical.

Logic Output. The Watchdog Output, WDO, goes low if WDI remains either high or low for longer than the watchdog timeout period. WDO is set high by the next transition at WDI. If WDI is unconnected or at midsupply, the watchdog timer is disabled and WDO remains high. WDO also goes high when LOW LINE goes low.

PIN CONFIGURATIONS

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Datasheet ID: ADM690AQ 517838