AD9627ABCPZ11-105

AD9627ABCPZ11-105 Datasheet

AD9627-11

Part	Datasheet
AD9627ABCPZ11-105	AD9627ABCPZ11-105 (pdf)

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SNR = dBc dBFS to 70 MHz 105 MSPS SFDR = 85 dBc to 70 MHz 105 MSPS Low power 600 mW 105 MSPS SNR = dBc dBFS to 70 MHz 150 MSPS SFDR = 84 dBc to 70 MHz 150 MSPS Low power 820 mW 150 MSPS V analog supply operation V to 3.3V CMOS output supply or V LVDS output supply Integer 1-to-8 input clock divider IF sampling frequencies to 450 MHz Internal ADC voltage reference Integrated ADC sample-and-hold inputs Flexible analog input range 1 V p-p to 2 V p-p Differential analog inputs with 650 MHz bandwidth ADC clock duty cycle stabilizer 95 dB channel isolation/crosstalk Serial port control User-configurable, built-in self-test BIST capability Energy-saving power-down modes Integrated receive features Fast detect/threshold bits Composite signal monitor Communications Diversity radio systems Multimode digital receivers 3G GSM, EDGE, WCDMA, CDMA2000, WiMAX, TD-SCDMA I/Q demodulation systems Smart antenna systems General-purpose software radios Broadband data applications 11-Bit, 105 MSPS/150 MSPS, V Dual Analog-to-Digital Converter AD9627-11 FUNCTIONAL BLOCK DIAGRAM SDIO/ SCLK/ AVDD DVDD FD 0:3 A DCS DFS CSB DRVDD CMOS OUTPUT BUFFER FD BITS/THRESHOLD DETECT VIN+A VREF SENSE CML RBIAS REF SELECT PROGRAMMING DATA SIGNAL MONITOR DIVIDE 1 TO 8 DUTY CYCLE STABILIZER DCO GENERATION CMOS OUTPUT BUFFER VIN+B AD9627-11 SIGNAL MONITOR DATA MULTICHIP FD BITS/THRESHOLD SIGNAL MONITOR SYNC DETECT INTERFACE D10A D0A CLK+ DCOA DCOB D10B D0B 07054-001 AGND SYNC FD 0:3 B SMI DRGND SDFS SCLK/ SDO/ NOTES PDWN OEB PIN NAMES ARE FOR THE CMOS PIN CONFIGURATION ONLY; SEE FIGURE 7 FOR LVDS PIN NAMES. Figure PRODUCT HIGHLIGHTS Configuration Using the 38 Hardware 38 Configuration Without the SPI 39 SPI Accessible 39 Memory Map 40 Reading the Memory Map Register Table............................... 40 Memory Map Register 41 Memory Map Register 44 Applications Information 47 Design Guidelines 47 Evaluation Board 48 Power Supplies 48 Input 48 Output Signals 48 Default Operation and Jumper Selection Settings................. 49 Alternative Clock Configurations 49 Alternative Analog Input Drive Configuration...................... 50 Schematics 51 Evaluation Board Layouts 61 Bill of 69 Outline Dimensions 71 Ordering Guide 71 0 Initial Version AD9627-11 AD9627-11 The AD9627-11 is a dual, 11-bit, 105 MSPS/150 MSPS analog-todigital converter ADC . The AD9627-11 is designed to support communications applications where low cost, small size, and versatility are desired. The dual ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth differential sample-and-hold analog input amplifiers supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance. The AD9627-11 has several functions that simplify the automatic gain control AGC function in the system receiver. The fast detect feature allows fast overrange detection by outputting four bits of input level information with very short latency. In addition, the programmable threshold detector allows monitoring of the incoming signal power using the four fast detect bits of the ADC with very low latency. If the input signal level exceeds the programmable threshold, the coarse upper threshold indicator goes high. Because this threshold indicator has very low latency, the user can quickly turn down the system gain to avoid an overrange condition. The second AGC-related function is the signal monitor. This block allows the user to monitor the composite magnitude of the incoming signal, which aids in setting the gain to optimize the dynamic range of the overall system. The ADC output data can be routed directly to the two external 11-bit output ports. These outputs can be set from V to V CMOS or V LVDS. Flexible power-down options allow significant power savings, when desired. Programming for setup and control is accomplished using a 3-bit SPI-compatible serial interface. The AD9627-11 is available in a 64-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C. AD9627-11 SPECIFICATIONS ADC DC AVDD = V, DVDD = V, DRVDD = V, maximum sample rate, VIN = dBFS differential input, V internal reference, DCS enabled, fast detect output pins disabled, and signal monitor disabled, unless otherwise noted. Table Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Gain Error Differential Nonlinearity DNL 1 Integral Nonlinearity INL 1 MATCHING CHARACTERISTIC Offset Error Gain Error TEMPERATURE DRIFT Offset Error Gain Error INTERNAL VOLTAGE REFERENCE Output Voltage Error 1 V Mode Load Regulation mA INPUT REFERRED NOISE VREF = V ANALOG INPUT Span, VREF = V Input Capacitance2 VREF INPUT RESISTANCE POWER SUPPLIES Supply Voltage AVDD, DVDD DRVDD CMOS Mode DRVDD LVDS Mode Supply Current IAVDD1, 3 IDVDD1, 3 IDRVDD1 V CMOS IDRVDD1 V CMOS IDRVDD1 V LVDS POWER CONSUMPTION DC Input Sine Wave Input1 DRVDD = V Sine Wave Input1 DRVDD = V Standby Power4 Power-Down Power Temperature Full Full 25°C Full 25°C 25°C 25°C Full Full 25°C 25°C Full Full Full Full ORDERING GUIDE Model AD9627BCPZ11-1501 AD9627BCPZ11-1051 AD962711-150EBZ1 AD962711-105EBZ1 Temperature Range −40°C to +85°C −40°C to +85°C Package Description 64-Lead Frame Chip Scale Package [LFCSP_VQ] 64-Lead Frame Chip Scale Package [LFCSP_VQ] Evaluation Board Evaluation Board Package Option CP-64-3 CP-64-3 1 Z = RoHS Compliant Part. AD9627-11 NOTES Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07054-0-9/09 A

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SNR = dBc dBFS to 70 MHz 105 MSPS SFDR = 85 dBc to 70 MHz 105 MSPS Low power 600 mW 105 MSPS SNR = dBc dBFS to 70 MHz 150 MSPS SFDR = 84 dBc to 70 MHz 150 MSPS Low power 820 mW 150 MSPS V analog supply operation V to 3.3V CMOS output supply or V LVDS
output supply Integer 1-to-8 input clock divider IF sampling frequencies to 450 MHz Internal ADC voltage reference Integrated ADC sample-and-hold inputs Flexible analog input range 1 V p-p to 2 V p-p Differential analog inputs with 650 MHz bandwidth ADC clock duty cycle stabilizer 95 dB channel isolation/crosstalk Serial port control User-configurable, built-in self-test BIST capability Energy-saving power-down modes Integrated receive features

Fast detect/threshold bits Composite signal monitor

Communications Diversity radio systems Multimode digital receivers 3G

GSM, EDGE, WCDMA, CDMA2000, WiMAX, TD-SCDMA I/Q demodulation systems Smart antenna systems General-purpose software radios Broadband data applications
11-Bit, 105 MSPS/150 MSPS, V Dual Analog-to-Digital Converter

AD9627-11

FUNCTIONAL BLOCK DIAGRAM

SDIO/ SCLK/ AVDD DVDD FD 0:3 A DCS DFS CSB DRVDD

CMOS OUTPUT BUFFER

FD BITS/THRESHOLD

DETECT

VIN+A VREF SENSE

CML RBIAS

REF SELECT

PROGRAMMING DATA

SIGNAL MONITOR

DIVIDE 1 TO 8

DUTY CYCLE STABILIZER

DCO GENERATION

CMOS OUTPUT BUFFER

VIN+B

AD9627-11

SIGNAL MONITOR DATA

MULTICHIP FD BITS/THRESHOLD SIGNAL MONITOR

SYNC

DETECT

INTERFACE

D10A D0A

CLK+ DCOA DCOB D10B D0B
07054-001

AGND SYNC

FD 0:3 B

SMI DRGND

SDFS SCLK/ SDO/

NOTES

PDWN OEB

PIN NAMES ARE FOR THE CMOS PIN CONFIGURATION ONLY;

SEE FIGURE 7 FOR LVDS PIN NAMES.

Figure

PRODUCT HIGHLIGHTS
Configuration Using the 38 Hardware 38 Configuration Without the SPI 39 SPI Accessible 39 Memory Map 40 Reading the Memory Map Register Table............................... 40 Memory Map Register 41 Memory Map Register 44 Applications Information 47 Design Guidelines 47 Evaluation Board 48 Power Supplies 48 Input 48 Output Signals 48 Default Operation and Jumper Selection Settings................. 49 Alternative Clock Configurations 49 Alternative Analog Input Drive Configuration...................... 50 Schematics 51 Evaluation Board Layouts 61 Bill of 69 Outline Dimensions 71 Ordering Guide 71
0 Initial Version

AD9627-11

AD9627-11

The AD9627-11 is a dual, 11-bit, 105 MSPS/150 MSPS analog-todigital converter ADC . The AD9627-11 is designed to support communications applications where low cost, small size, and versatility are desired.

The dual ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth differential sample-and-hold analog input amplifiers supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.

The AD9627-11 has several functions that simplify the automatic gain control AGC function in the system receiver. The fast detect feature allows fast overrange detection by outputting four bits of input level information with very short latency.

In addition, the programmable threshold detector allows monitoring of the incoming signal power using the four fast detect bits of the ADC with very low latency. If the input signal level exceeds
the programmable threshold, the coarse upper threshold indicator goes high. Because this threshold indicator has very low latency, the user can quickly turn down the system gain to avoid an overrange condition.

The second AGC-related function is the signal monitor. This block allows the user to monitor the composite magnitude of the incoming signal, which aids in setting the gain to optimize the dynamic range of the overall system.

The ADC output data can be routed directly to the two external 11-bit output ports. These outputs can be set from V to V CMOS or V LVDS.

Flexible power-down options allow significant power savings, when desired.

Programming for setup and control is accomplished using a 3-bit SPI-compatible serial interface.

The AD9627-11 is available in a 64-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C.

AD9627-11

SPECIFICATIONS

ADC DC

AVDD = V, DVDD = V, DRVDD = V, maximum sample rate, VIN = dBFS differential input, V internal reference, DCS enabled, fast detect output pins disabled, and signal monitor disabled, unless otherwise noted.

Table

Parameter RESOLUTION ACCURACY

No Missing Codes Offset Error Gain Error Differential Nonlinearity DNL 1

Integral Nonlinearity INL 1

MATCHING CHARACTERISTIC Offset Error Gain Error

TEMPERATURE DRIFT Offset Error Gain Error

INTERNAL VOLTAGE REFERENCE Output Voltage Error 1 V Mode Load Regulation mA

INPUT REFERRED NOISE VREF = V

ANALOG INPUT Span, VREF = V Input Capacitance2

VREF INPUT RESISTANCE POWER SUPPLIES

Supply Voltage AVDD, DVDD DRVDD CMOS Mode DRVDD LVDS Mode

Supply Current IAVDD1, 3 IDVDD1, 3 IDRVDD1 V CMOS IDRVDD1 V CMOS IDRVDD1 V LVDS

POWER CONSUMPTION DC Input Sine Wave Input1 DRVDD = V Sine Wave Input1 DRVDD = V Standby Power4 Power-Down Power

Temperature Full

Full 25°C Full 25°C
25°C 25°C

Full

Full 25°C
25°C

Full

Full

Full

Full
ORDERING GUIDE

Model AD9627BCPZ11-1501 AD9627BCPZ11-1051 AD962711-150EBZ1 AD962711-105EBZ1

Temperature Range −40°C to +85°C −40°C to +85°C

Package Description 64-Lead Frame Chip Scale Package [LFCSP_VQ] 64-Lead Frame Chip Scale Package [LFCSP_VQ] Evaluation Board Evaluation Board

Package Option CP-64-3 CP-64-3
1 Z = RoHS Compliant Part.

AD9627-11 NOTES

Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.

D07054-0-9/09 A

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived AD9627ABCPZ11-105 Datasheet file may be downloaded here without warranties.

Datasheet ID: AD9627ABCPZ11-105 517776