AD808-622BRRL

AD808-622BRRL Datasheet


AD808

Part Datasheet
AD808-622BRRL AD808-622BRRL AD808-622BRRL (pdf)
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a Fiber Optic Receiver with Quantizer and Clock Recovery and Data Retiming

AD808

FEATURES Meets CCITT G.958 Requirements
for STM-4 A Meets Bellcore TR-NWT-000253 Requirements for OC-12 Output Jitter Degrees RMS 622 Mbps Clock Recovery and Data Retiming Accepts NRZ Data, No Preamble Required Phase-Locked Loop Type Clock

No Crystal Required Quantizer Sensitivity 4 mV Level Detect Range 10 mV to 40 mV, Programmable Single Supply Operation +5 V or V Low Power 400 mW 10 KH ECL/PECL Compatible Output Package 16-Lead Narrow 150 mil SOIC

PRODUCT DESCRIPTION The AD808 provides the receiver functions of data quantization, signal level detect, clock recovery and data retiming for 622 Mbps NRZ data. The device, together with a PIN diode/preamplifier combination, can be used for a highly integrated, low cost, low power SONET OC-12 or SDH STM-4 fiber optic receiver.

The receiver front end signal level detect circuit indicates when the input signal level has fallen below a user adjustable threshold. The threshold is set with a single external resistor. The signal level detect circuit 3 dB optical hysteresis prevents chatter at the signal level detect output.

The PLL has a factory trimmed VCO center frequency and a frequency acquisition control loop that combine to guarantee
frequency acquisition without false lock. This eliminates a reliance on external components such as a crystal or a SAW filter, to aid frequency acquisition.

The AD808 acquires frequency and phase lock on input data using two control loops that work without requiring external control. The frequency acquisition control loop initially acquires the frequency of the input data, acquiring frequency lock on random or scrambled data without the need for a preamble. At frequency lock, the frequency error is zero and the frequency detector has no further effect. The phase acquisition control loop then works to ensure that the output phase tracks the input phase. A patented phase detector has virtually eliminated pattern jitter throughout the AD808.

The device VCO uses a ring oscillator architecture and patented low noise design techniques. Jitter is degrees rms. This low jitter results from using a fully differential signal architecture, Power Supply Rejection Ratio circuitry and a dielectrically isolated process that provides immunity from extraneous signals on the IC. The device can withstand hundreds of millivolts of power supply noise without an effect on jitter performance.

The user sets the jitter peaking and acquisition time of the PLL by choosing a damping factor capacitor whose value determines loop damping. CCITT G.958 Type A jitter transfer requirements can easily be met with a damping factor of 5 or greater.

Device design guarantees that the clock output frequency will drift by less than 20% in the absence of input data transitions. Shorting the damping factor capacitor, CD, brings the clock output frequency to the VCO center frequency.

The AD808 consumes 400 mW and operates from a single power supply at either +5 V or V.

FUNCTIONAL BLOCK DIAGRAM

QUANTIZER PIN NIN

THRADJ

SIGNAL LEVEL DETECTOR

LEVEL DETECT COMPARATOR/ BUFFER

CF1 CF2

COMPENSATING ZERO

PHASE-LOCKED LOOP

FDET

AD808

RETIMING DEVICE

LOOP FILTER

CLKOUTP CLKOUTN

DATAOUTP DATAOUTN

SDOUT

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel 781/329-4700

World Wide Web Site:

Fax 781/326-8703

Analog Devices, Inc., 1998

TA = TMIN to TMAX, VS = VMIN to VMAX, CD = unless otherwise noted

Parameter CHARACTERISTICS

Input Voltage Range Input Sensitivity, VSENSE Input Overdrive, VOD Input Offset Voltage Input Current Input RMS Noise Input Peak-to-Peak Noise CHARACTERISTICS Upper dB Bandwidth Input Resistance Input Capacitance Pulsewidth Distortion LEVEL DETECT Level Detect Range

Response Time Hysteresis Electrical

SDOUT Output Logic High SDOUT Output Logic Low PHASE-LOCKED LOOP NOMINAL CENTER FREQUENCY CAPTURE RANGE TRACKING RANGE STATIC PHASE ERROR See Figure 7 SETUP TIME tSU HOLD TIME tH PHASE DRIFT JITTER

JITTER TOLERANCE
ORDERING GUIDE

Temperature Range
to +85°C to +85°C to +85°C

Package Description
16-Pin Narrowbody SOIC 750 Pieces, 7" Reel 2500 Pieces, 13" Reel

Package Option

R-16A R-16A R-16A

CAUTION ESD electrostatic discharge sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD808 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

AD808

DEFINITION OF TERMS Maximum, Minimum and Typical Specifications for every parameter are derived from statistical analyses of data taken on multiple devices from multiple wafer lots. Typical specifications are the mean of the distribution of the data for that parameter. If a parameter has a maximum or a minimum , that value is calculated by adding to or subtracting from the mean six times the standard deviation of the distribution. This procedure is intended to tolerate production variations if the mean shifts by standard deviations, the remaining standard deviations still provide a failure rate of only parts per million. For all tested parameters, the test limits are guardbanded to account for tester variation to thus guarantee that no device is shipped outside of data sheet specifications.

Input Sensitivity and Input Overdrive Sensitivity and Overdrive specifications for the Quantizer involve offset voltage, gain and noise. The relationship between the logic output of the quantizer and the analog voltage input is shown in Figure

For sufficiently large positive input voltage the output is always Logic 1 and similarly, for negative inputs, the output is always Logic However, the transitions between output Logic Levels 1 and 0 are not at precisely defined input voltage levels, but occur over a range of input voltages. Within this Zone of Confusion, the output may be either 1 or 0, or it may even fail to attain a valid logic state. The width of this zone is determined by the input voltage noise of the quantizer mV at the 1 x confidence level . The center of the Zone of Confusion is the quantizer input offset voltage 1 mV typ . Input Overdrive is the magnitude of signal required to guarantee correct logic level with 1 x confidence level.

With a single-ended PIN-TIA Figure 3 , ac coupling is used and the inputs to the Quantizer are dc biased at some commonmode potential. Observing the Quantizer input with an oscilloscope probe at the point indicated shows a binary signal with average value equal to the common-mode potential and instantaneous values both above and below the average value. It is convenient to measure the peak-to-peak amplitude of this signal and call the minimum required value the Quantizer Sensitivity. Referring to Figure 1, since both positive and negative offsets need to be accommodated, the Sensitivity is twice the Overdrive. The AD808 Quantizer has 4 mV Sensitivity typical.

With a differential TIA Figure 3 , Sensitivity seems to improve from observing the Quantizer input with an oscilloscope probe. This is an illusion caused by the use of a single-ended probe. A 2 mV peak-to-peak signal appears to drive the AD808 Quantizer. However, the single-ended probe measures only half the signal. The true Quantizer input signal is twice this value since the other Quantizer input is a complementary signal to the signal being observed.

Response Time Response time is the delay between removal of the input signal and indication of Loss of Signal LOS at SDOUT. The response time of the AD808 µs maximum is much faster than the SONET/SDH requirement 3 µs response time 100 µs . In practice, the time constant of the ac coupling at the Quantizer input determines the LOS response time.

Nominal Center Frequency This is the frequency at which the VCO will oscillate with the loop damping capacitor, CD, shorted.

Tracking Range This is the range of input data rates over which the AD808 will remain in lock.

Capture Range This is the range of input data rates over which the AD808 will acquire lock.

Static Phase Error This is the steady-state phase difference, in degrees, between the recovered clock sampling edge and the optimum sampling instant, which is assumed to be halfway between the rising and falling edges of a data bit. Gate delays between the signals that define static phase error, and IC input and output signals prohibit direct measurement of static phase error.

Data Transition Density, This is a measure of the number of data transitions, from “0” to “1” and from “1” to “0,” over many clock periods. is the ratio 0 1 of data transitions to bit periods.

Jitter This is the dynamic displacement of digital signal edges from their long term average positions, measured in degrees rms or Unit Intervals UI . Jitter on the input data can cause dynamic phase errors on the recovered clock sampling edge. Jitter on the recovered clock causes jitter on the retimed data.

Output Jitter This is the jitter on the retimed data, in degrees rms, due to a specific pattern or some pseudorandom input data sequence PRN Sequence .

Jitter Tolerance Jitter Tolerance is a measure of the AD808’s ability to track a jittery input data signal. Jitter on the input data is best thought of as phase modulation, and is usually specified in unit intervals.

The PLL must provide a clock signal that tracks the phase modulation in order to accurately retime jittered data. In order for the VCO output to have a phase modulation that tracks the input jitter, some modulation signal must be generated at the output of the phase detector. The modulation output from the phase detector can only be produced by a phase error between its data input and its clock input. Hence, the PLL can never perfectly track jittered data. However, the magnitude of the phase error depends on the gain around the loop. At low frequencies, the integrator of the AD808 PLL provides very high gain, and thus very large jitter can be tracked with small phase errors between input data and recovered clock. At frequencies closer to the loop bandwidth, the gain of the integrator is much smaller, and thus less input jitter can be tolerated. The AD808 output will have a bit error rate less than 1 x when in lock and retiming input data that has the CCITT G.958 specified jitter applied to it.

Jitter Transfer Refer to Figure 14 The AD808 exhibits a low-pass filter response to jitter applied to its input data.

Bandwidth This describes the frequency at which the AD808 attenuates sinusoidal input jitter by 3 dB.

Peaking This describes the maximum jitter gain of the AD808 in dB.

AD808

Damping Factor, ζ Damping factor, ζ describes the compensation of the second order PLL. A larger value of ζ corresponds to more damping and less peaking in the jitter transfer function.

Acquisition Time This is the transient time, measured in bit periods, required for the AD808 to lock onto input data from its free-running state.

Clock Duty Cycle Symmetry is calculated as 100 x on time /period, where on time equals the time that the clock signal is greater than the midpoint between its “0” level and its “1” level.

INPUT
4mVp-p

SCOPE PROBE AD808 QUANTIZER

BINARY OUTPUT
a. Single-Ended Input Application
2mVp-p
+INPUT

SCOPE PROBE AD808 QUANTIZER
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Datasheet ID: AD808-622BRRL 517749