AD5372BCPZ-RL7

AD5372BCPZ-RL7 Datasheet

AD5372/AD5373

Part	Datasheet
AD5372BCPZ-RL7	AD5372BCPZ-RL7 (pdf)

Related Parts	Information
AD5373BCPZ-RL7	AD5373BCPZ-RL7

PDF Datasheet Preview
32-Channel, 16-/14-Bit, Serial Input, Voltage Output DAC AD5372/AD5373 32-channel DAC in a 64-lead LQFP and 64-lead LFCSP AD5372/AD53731 guaranteed monotonic to 16/14 bits Maximum output voltage span of 4 x VREF 20 V Nominal output voltage range of −4 V to +8 V Multiple, independent output voltage spans available System calibration function allowing user-programmable offset and gain Channel grouping and addressing features Thermal shutdown function DSP/microcontroller-compatible serial interface SPI serial interface V to V JEDEC-compliant digital levels Digital reset Clear function to user-defined SIGGNDx Simultaneous update of DAC outputs Level setting in automatic test equipment ATE Variable optical attenuators VOA Optical switches Industrial control systems Instrumentation DVCC VDD VSS AGND DGND FUNCTIONAL BLOCK DIAGRAM LDAC CONTROL REGISTER n = 16 FOR AD5372 n = 14 FOR AD5373 A/B SELECT 8 REGISTER n X1 REGISTER n M REGISTER n C REGISTER TO MUX 2s A/B MUX X2A REGISTER X2B REGISTER MUX 2 OFS0 OFFSET REGISTER DAC 0 BUFFER BUFFER GROUP 0 DAC 0 REGISTER DAC 0 OUTPUT BUFFER AND POWER- DOWN CONTROL SYNC SDI SCLK SDO BUSY RESET CLR SERIAL INTERFACE STATE MACHINE X1 REGISTER M REGISTER C REGISTER A/B SELECT 8 Reference Selection 17 18 Additional 19 Reset Function 19 Clear Function 19 BUSY and LDAC 19 Power-Down 20 Thermal Shutdown Function 20 Toggle 20 Serial Interface 21 SPI Write Mode 21 SPI Readback Mode 21 Register Update Rates 21 Channel Addressing and Special Modes 22 Special Function 23 Applications Information 24 Power Supply Decoupling 24 Power Supply Sequencing 24 Interfacing Examples 24 Outline Dimensions 25 Ordering Guide 26 Changes to Absolute Maximum Ratings Section..........................9 Changes to Pin Configuration and Function Descriptions 10 Changes to Reset Function 18 0 Initial Version The AD5372/AD5373 contain 32 16-/14-bit DACs in 64-lead LQFP and LFCSP packages. The devices provide buffered voltage outputs with a nominal span of 4x the reference voltage. The gain and offset of each DAC can be independently trimmed to remove errors. For even greater flexibility, the device is divided into four groups of eight DACs. Two offset DACs allow the output range of the groups to be altered. Group 0 can be adjusted by Offset DAC 0, and Group 1 to Group 3 can be adjusted by Offset DAC The AD5372/AD5373 offer guaranteed operation over a wide supply range VSS from V to V and VDD from 9 V to V. The output amplifier headroom requirement is V operating with a load current of 1 mA. Table High Channel Count Bipolar DACs Model Resolution Bits Nominal Output Span AD5360 4 x VREF 20 V AD5361 4 x VREF 20 V AD5362 4 x VREF 20 V AD5363 4 x VREF 20 V AD5370 4 x VREF 12 V AD5371 4 x VREF 12 V AD5372 4 x VREF 12 V AD5373 4 x VREF 12 V AD5378 AD5379 AD5372/AD5373 The AD5372/AD5373 have a high speed serial interface that is compatible with SPI, QSPI , MICROWIRE , and DSP interface standards and can handle clock speeds of up to 50 MHz. The DAC registers are updated on reception of new data. All the outputs can be updated simultaneously by taking the LDAC input low. Each channel has a programmable gain and an offset adjust register. Each DAC output is gained and buffered on chip with respect to an external SIGGNDx input. The DAC outputs can also be switched to SIGGNDx via the CLR pin. Output Channels 16 8 40 32 40 Linearity Error LSB ±4 ±1 ±4 ±1 ±4 ±1 ±4 ±1 ±3 ±3 AD5372/AD5373 SPECIFICATIONS DVCC = V to V VDD = 9 V to V VSS = V to −8 V VREF0 = VREF1 = 3 V AGND = DGND = SIGGNDx = 0 V CL = open circuit RL = open circuit gain M , offset C , and DAC offset registers at default values all specifications TMIN to TMAX, unless otherwise noted. Table Parameter ACCURACY Resolution Integral Nonlinearity INL Differential Nonlinearity DNL Zero-Scale Error Full-Scale Error Gain Error Zero-Scale Error2 Full-Scale Error2 Span Error of Offset DAC VOUTx Temperature Coefficient DC Crosstalk2 REFERENCE INPUTS VREF0, VREF1 2 VREFx Input Current VREFx Range SIGGND INPUTS SIGGND0 TO SIGGND3 2 DC Input Impedance Input Range SIGGNDx Gain OUTPUT CHARACTERISTICS2 Output Voltage Range Nominal Output Voltage Range Short-Circuit Current Load Current Capacitive Load DC Output Impedance DIGITAL INPUTS Input High Voltage Input Low Voltage Input Current CLR High Impedance Leakage Current Input Capacitance2 DIGITAL OUTPUTS SDO, BUSY Output Low Voltage Output High Voltage SDO High Impedance Leakage Current High Impedance Output Capacitance2 AD53721 B Version ORDERING GUIDE Model1 Temperature Range AD5372BSTZ −40°C to +85°C AD5372BSTZ-REEL −40°C to +85°C AD5372BCPZ −40°C to +85°C AD5372BCPZ-RL7 −40°C to +85°C AD5373BSTZ −40°C to +85°C AD5373BSTZ-REEL −40°C to +85°C AD5373BCPZ −40°C to +85°C AD5373BCPZ-RL7 −40°C to +85°C EVAL-AD5372EBZ EVAL-AD5373EBZ 1 Z = RoHS Compliant Part. Package Description 64-Lead Low Profile Quad Flat Package LQFP 64-Lead Low Profile Quad Flat Package LQFP 64-Lead Frame Chip Scale Package LFCSP_VQ 64-Lead Frame Chip Scale Package LFCSP_VQ 64-Lead Low Profile Quad Flat Package LQFP 64-Lead Low Profile Quad Flat Package LQFP 64-Lead Frame Chip Scale Package LFCSP_VQ 64-Lead Frame Chip Scale Package LFCSP_VQ Evaluation Board Evaluation Board Package Option ST-64-2 ST-64-2 CP-64-3 CP-64-3 ST-64-2 ST-64-2 CP-64-3 CP-64-3 NOTES AD5372/AD5373 AD5372/AD5373 NOTES Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05815-0-7/11 C

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32-Channel, 16-/14-Bit, Serial Input, Voltage Output DAC

AD5372/AD5373
32-channel DAC in a 64-lead LQFP and 64-lead LFCSP AD5372/AD53731 guaranteed monotonic to 16/14 bits Maximum output voltage span of 4 x VREF 20 V Nominal output voltage range of −4 V to +8 V Multiple, independent output voltage spans available System calibration function allowing user-programmable
offset and gain Channel grouping and addressing features Thermal shutdown function DSP/microcontroller-compatible serial interface SPI serial interface

V to V JEDEC-compliant digital levels Digital reset Clear function to user-defined SIGGNDx Simultaneous update of DAC outputs

Level setting in automatic test equipment ATE Variable optical attenuators VOA Optical switches Industrial control systems Instrumentation

DVCC VDD VSS AGND DGND

FUNCTIONAL BLOCK DIAGRAM

LDAC

CONTROL REGISTER
n = 16 FOR AD5372 n = 14 FOR AD5373

A/B SELECT 8 REGISTER
n X1 REGISTER
n M REGISTER
n C REGISTER

TO MUX 2s

A/B MUX

X2A REGISTER X2B REGISTER

MUX 2

OFS0

OFFSET

REGISTER

DAC 0

BUFFER

BUFFER

GROUP 0

DAC 0

REGISTER

DAC 0

OUTPUT BUFFER AND POWER-

DOWN CONTROL

SYNC SDI

SCLK SDO

BUSY

RESET CLR

SERIAL INTERFACE

STATE MACHINE

X1 REGISTER

M REGISTER

C REGISTER

A/B SELECT 8
Reference Selection 17 18 Additional 19 Reset Function 19 Clear Function 19 BUSY and LDAC 19 Power-Down 20 Thermal Shutdown Function 20 Toggle 20 Serial Interface 21 SPI Write Mode 21 SPI Readback Mode 21 Register Update Rates 21 Channel Addressing and Special Modes 22 Special Function 23 Applications Information 24 Power Supply Decoupling 24 Power Supply Sequencing 24 Interfacing Examples 24 Outline Dimensions 25 Ordering Guide 26

Changes to Absolute Maximum Ratings Section..........................9 Changes to Pin Configuration and Function Descriptions 10 Changes to Reset Function 18
0 Initial Version

The AD5372/AD5373 contain 32 16-/14-bit DACs in 64-lead LQFP and LFCSP packages. The devices provide buffered voltage outputs with a nominal span of 4x the reference voltage. The gain and offset of each DAC can be independently trimmed to remove errors. For even greater flexibility, the device is divided into four groups of eight DACs. Two offset DACs allow the output range of the groups to be altered. Group 0 can be adjusted by Offset DAC 0, and Group 1 to Group 3 can be adjusted by Offset DAC

The AD5372/AD5373 offer guaranteed operation over a wide supply range VSS from V to V and VDD from 9 V to V. The output amplifier headroom requirement is V operating with a load current of 1 mA.

Table High Channel Count Bipolar DACs

Model

Resolution Bits Nominal Output Span

AD5360
4 x VREF 20 V

AD5361
4 x VREF 20 V

AD5362
4 x VREF 20 V

AD5363
4 x VREF 20 V

AD5370
4 x VREF 12 V

AD5371
4 x VREF 12 V

AD5372
4 x VREF 12 V

AD5373
4 x VREF 12 V

AD5378

AD5379

AD5372/AD5373

The AD5372/AD5373 have a high speed serial interface that is compatible with SPI, QSPI , MICROWIRE , and DSP interface standards and can handle clock speeds of up to 50 MHz. The DAC registers are updated on reception of new data. All the outputs can be updated simultaneously by taking the LDAC input low. Each channel has a programmable gain and an offset adjust register. Each DAC output is gained and buffered on chip with respect to an external SIGGNDx input. The DAC outputs can also be switched to SIGGNDx via the CLR pin.

Output Channels 16 8 40 32 40

Linearity Error LSB ±4 ±1 ±4 ±1 ±4 ±1 ±4 ±1 ±3 ±3

AD5372/AD5373

SPECIFICATIONS

DVCC = V to V VDD = 9 V to V VSS = V to −8 V VREF0 = VREF1 = 3 V AGND = DGND = SIGGNDx = 0 V CL = open circuit RL = open circuit gain M , offset C , and DAC offset registers at default values all specifications TMIN to TMAX, unless otherwise noted.

Table

Parameter ACCURACY

Resolution Integral Nonlinearity INL Differential Nonlinearity DNL

Zero-Scale Error Full-Scale Error Gain Error Zero-Scale Error2 Full-Scale Error2 Span Error of Offset DAC VOUTx Temperature Coefficient DC Crosstalk2

REFERENCE INPUTS VREF0, VREF1 2 VREFx Input Current VREFx Range

SIGGND INPUTS SIGGND0 TO SIGGND3 2 DC Input Impedance Input Range SIGGNDx Gain

OUTPUT CHARACTERISTICS2 Output Voltage Range

Nominal Output Voltage Range Short-Circuit Current Load Current Capacitive Load DC Output Impedance DIGITAL INPUTS Input High Voltage

Input Low Voltage Input Current CLR High Impedance Leakage Current Input Capacitance2 DIGITAL OUTPUTS SDO, BUSY Output Low Voltage Output High Voltage SDO High Impedance Leakage Current High Impedance Output Capacitance2

AD53721 B Version
ORDERING GUIDE

Model1

Temperature Range

AD5372BSTZ
−40°C to +85°C

AD5372BSTZ-REEL −40°C to +85°C

AD5372BCPZ
−40°C to +85°C

AD5372BCPZ-RL7
−40°C to +85°C

AD5373BSTZ
−40°C to +85°C

AD5373BSTZ-REEL −40°C to +85°C

AD5373BCPZ
−40°C to +85°C

AD5373BCPZ-RL7
−40°C to +85°C

EVAL-AD5372EBZ

EVAL-AD5373EBZ
1 Z = RoHS Compliant Part.

Package Description 64-Lead Low Profile Quad Flat Package LQFP 64-Lead Low Profile Quad Flat Package LQFP 64-Lead Frame Chip Scale Package LFCSP_VQ 64-Lead Frame Chip Scale Package LFCSP_VQ 64-Lead Low Profile Quad Flat Package LQFP 64-Lead Low Profile Quad Flat Package LQFP 64-Lead Frame Chip Scale Package LFCSP_VQ 64-Lead Frame Chip Scale Package LFCSP_VQ Evaluation Board Evaluation Board

Package Option ST-64-2 ST-64-2 CP-64-3 CP-64-3 ST-64-2 ST-64-2 CP-64-3 CP-64-3

NOTES

AD5372/AD5373

AD5372/AD5373 NOTES

Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.

D05815-0-7/11 C

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Datasheet ID: AD5372BCPZ-RL7 517707