TSL208R

TSL208R Datasheet

TSL208R

Part	Datasheet
TSL208R	TSL208R (pdf)

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TSL208R 512 y 1 LINEAR SENSOR ARRAY r TAOS031G − AUGUST 2011 D 512 x 1 Sensor-Element Organization D 200 Dots-Per-Inch DPI Sensor Pitch D High Linearity and Uniformity D Wide Dynamic Range 2000:1 66 dB D Output Referenced to Ground D Low Image Lag Typ D Operation to 5 MHz D Single 5-V Supply D Replacement for TSL208 The TSL208R linear sensor array consists of a 512 x 1 array of photodiodes and associated charge amplifier circuitry. The pixels measure 120 um H by 70 um W with 125-um center-to-center spacing and 55-um spacing between pixels. Operation is simplified by internal control logic that requires only a serial-input SI signal and a clock. TOP VIEW 1 VDD 2 SI 3 CLK 4 AO 5 GND 6 SO 7 VDD The TSL208R is intended for use in a wide variety of applications including mark detection and code reading, optical character recognition OCR and contact imaging, edge detection and positioning as well as optical linear and rotary encoding. Functional Block Diagram Pixel 1 1 Integrator S1 2 Reset Sample/ Output Pixel 2 Pixel 3 Pixel 512 Analog Bus Output Amplifier 1 VDD RL 330 W 5 GND Switch Control Logic Gain Trim Q512 3 CLK 512-Bit Shift Register The LUMENOLOGY r Company Texas Advanced Optoelectronic Solutions Inc. 1001 Klein Road S Suite 300 S Plano, TX 75074 S 972r 673-0759 Copyright E 2011, TAOS Inc. 1 TSL208R 512 y 1 LINEAR SENSOR ARRAY TAOS031G − AUGUST 2011 Terminal Functions TERMINAL NAME NO. O Analog output. I Clock. The clock controls the charge transfer, pixel output and reset. I Ground substrate . All voltages are referenced to the substrate. I Serial input. SI defines the start of the data out sequence. O Serial output. SO signals the end of the data out sequence. I Supply voltage for both analog and digital circuits. Detailed Description The sensor consists of 512 photodiodes arranged in a linear array. Light energy impinging on a photodiode generates photocurrent, which is integrated by the active integration circuitry associated with that pixel. During the integration period, a sampling capacitor connects to the output of the integrator through an analog switch. The amount of charge accumulated at each pixel is directly proportional to the light intensity and the integration time. The integration time is the interval between two consecutive output periods. The output and reset of the integrators is controlled by a 512-bit shift register and reset logic. An output cycle is initiated by clocking in a logic 1 on SI for one positive going clock edge see Figures1 and As the SI pulse is clocked through the 512-bit shift register, the charge on the sampling capacitor of each pixel is sequentially connected to a charge-coupled output amplifier that generates a voltage output, AO. When the bit position goes low, the pixel integrator is reset. On the 513th clock rising edge, the SI pulse is clocked out of the shift register and the output assumes a high-impedance state. Note that this 513th clock pulse is required to terminate the output of the 512th pixel and return the internal logic to a known state. A subsequent SI pulse can be presented as early as the 514th clock pulse, thereby initiating another pixel output cycle. The voltage developed at analog output AO is given by: where:

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TSL208R
512 y 1 LINEAR SENSOR ARRAY
r TAOS031G − AUGUST 2011

D 512 x 1 Sensor-Element Organization D 200 Dots-Per-Inch DPI Sensor Pitch D High Linearity and Uniformity D Wide Dynamic Range 2000:1 66 dB D Output Referenced to Ground D Low Image Lag Typ D Operation to 5 MHz D Single 5-V Supply D Replacement for TSL208

The TSL208R linear sensor array consists of a 512 x 1 array of photodiodes and associated charge amplifier circuitry. The pixels measure 120 um H by 70 um W with 125-um center-to-center spacing and 55-um spacing between pixels. Operation is simplified by internal control logic that requires only a serial-input SI signal and a clock.

TOP VIEW
1 VDD 2 SI 3 CLK 4 AO 5 GND 6 SO 7 VDD

The TSL208R is intended for use in a wide variety of applications including mark detection and code reading, optical character recognition OCR and contact imaging, edge detection and positioning as well as optical linear and rotary encoding.

Functional Block Diagram

Pixel 1
1 Integrator S1 2 Reset

Sample/

Output

Pixel 2

Pixel 3

Pixel 512

Analog Bus

Output Amplifier
1 VDD

RL 330 W
5 GND

Switch Control Logic

Gain Trim

Q512
3 CLK
512-Bit Shift Register

The LUMENOLOGY r Company

Texas Advanced Optoelectronic Solutions Inc.
1001 Klein Road S Suite 300 S Plano, TX 75074 S 972r 673-0759

Copyright E 2011, TAOS Inc. 1

TSL208R 512 y 1 LINEAR SENSOR ARRAY

TAOS031G − AUGUST 2011

Terminal Functions

TERMINAL

NAME NO.

O Analog output. I Clock. The clock controls the charge transfer, pixel output and reset. I Ground substrate . All voltages are referenced to the substrate. I Serial input. SI defines the start of the data out sequence. O Serial output. SO signals the end of the data out sequence. I Supply voltage for both analog and digital circuits.

Detailed Description

The sensor consists of 512 photodiodes arranged in a linear array. Light energy impinging on a photodiode generates photocurrent, which is integrated by the active integration circuitry associated with that pixel. During the integration period, a sampling capacitor connects to the output of the integrator through an analog switch. The amount of charge accumulated at each pixel is directly proportional to the light intensity and the integration time. The integration time is the interval between two consecutive output periods.

The output and reset of the integrators is controlled by a 512-bit shift register and reset logic. An output cycle is initiated by clocking in a logic 1 on SI for one positive going clock edge see Figures1 and As the SI pulse is clocked through the 512-bit shift register, the charge on the sampling capacitor of each pixel is sequentially connected to a charge-coupled output amplifier that generates a voltage output, AO. When the bit position goes low, the pixel integrator is reset. On the 513th clock rising edge, the SI pulse is clocked out of the shift register and the output assumes a high-impedance state. Note that this 513th clock pulse is required to terminate the output of the 512th pixel and return the internal logic to a known state. A subsequent SI pulse can be presented as early as the 514th clock pulse, thereby initiating another pixel output cycle.

The voltage developed at analog output AO is given by:
where:

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Datasheet ID: TSL208R 519829