EP1S10B672I7

EP1S10B672I7 Datasheet

Table ● Note 1 was added to Table ● Added tSU_R and tSU_C rows in Table ● Changed Table title from “EP1S10 Column Pin Fast Regional

Part	Datasheet
EP1S10B672I7	EP1S10B672I7 (pdf)

Related Parts	Information
EP1S30F780C6DM	EP1S30F780C6DM
EP1S60F1020C6NAA	EP1S60F1020C6NAA
EP1S40F1020I6AA	EP1S40F1020I6AA
EP1S40F1020C5GA	EP1S40F1020C5GA
EP1S40F1020C5DM	EP1S40F1020C5DM
EP1S40F1020C5AA	EP1S40F1020C5AA
EP1S30F780C7AA	EP1S30F780C7AA
EP1S30F780C6GA	EP1S30F780C6GA
EP1S40F1020I6GB	EP1S40F1020I6GB
EP1S30F1020I6GA	EP1S30F1020I6GA
EP1S30F1020C6NGA	EP1S30F1020C6NGA
EP1S25F672C7NGA	EP1S25F672C7NGA
EP1S25F672C7DM	EP1S25F672C7DM
EP1S25F672C7AA	EP1S25F672C7AA
EP1S25F1020C6NGA	EP1S25F1020C6NGA
EP1S20F780C6GA	EP1S20F780C6GA
EP1S10F672C7AA	EP1S10F672C7AA
EP1S60F1020C6NGB	EP1S60F1020C6NGB
EP1S20F484C6GA	EP1S20F484C6GA
EP1S80B956C6AA	EP1S80B956C6AA
EP1S80B956C6AB	EP1S80B956C6AB
EP1S80F1020C7GA	EP1S80F1020C7GA
EP1S80F1020C7NGA	EP1S80F1020C7NGA
EP1S80F1020I7NGA	EP1S80F1020I7NGA
EP1S80F1508C6AA	EP1S80F1508C6AA
EP1S80F1508I6	EP1S80F1508I6
EP1S60F1020I6GB	EP1S60F1020I6GB
EP1S40F1508C6NGA	EP1S40F1508C6NGA

PDF Datasheet Preview
Stratix Device Handbook, Volume 1 101 Innovation Drive San Jose, CA 95134 408 544-7000 S5V1-3.4 Copyright 2006 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. Altera Corporation Contents About This Handbook ix How to Find Information ix How to Contact Altera ix Typographic Conventions x Section I. Stratix Device Family Data Sheet Chapter Introduction Introduction Features Chapter Stratix Architecture Functional Description Logic Array Blocks LAB Interconnects LAB Control Signals Logic Elements LUT Chain & Register Chain addnsub Signal LE Operating Modes Clear & Preset Logic Control MultiTrack Interconnect TriMatrix Memory Modes Clear Signals Parity Bit Support Shift Register Support Memory Block Size Independent Clock Mode Input/Output Clock Mode Read/Write Clock Mode Single-Port Mode Multiplier Block Adder/Output Blocks Modes of Operation Altera Corporation Contents Stratix Device Handbook, Volume 1 DSP Block Interface PLLs & Clock Networks Global & Hierarchical Clocking Enhanced & Fast PLLs Enhanced PLLs Fast PLLs I/O Structure Double-Data Rate I/O Pins External RAM Interfacing Programmable Drive Strength Open-Drain Output Slew-Rate Control Bus Hold Programmable Pull-Up Resistor Advanced I/O Standard Support Differential On-Chip Termination MultiVolt I/O Interface High-Speed Differential I/O Support Dedicated Circuitry Byte Alignment Power Sequencing & Hot Socketing Chapter Configuration & Testing IEEE Std. JTAG Boundary-Scan Support SignalTap II Embedded Logic Analyzer Configuration Operating Modes Configuring Stratix FPGAs with JRunner Configuration Schemes Partial Reconfiguration Remote Update Configuration Modes Stratix Automated Single Event Upset SEU Detection Custom-Built Circuitry Software Interface Temperature Sensing Diode Chapter DC & Switching Characteristics Operating Conditions Power Consumption Timing Model Preliminary & Final Timing Performance Internal Timing Parameters External Timing Parameters Stratix External I/O Timing I/O Timing Measurement Methodology External I/O Delay Parameters Altera Corporation Contents Contents Maximum Input & Output Clock Rates High-Speed I/O Specification PLL Specifications DLL Specifications Chapter Reference & Ordering Information Software Device Pin-Outs Ordering Information Index Altera Corporation Contents Stratix Device Handbook, Volume 1 Altera Corporation Chapter Introduction July 2005 Part number S51001-3.2 Chapter Stratix Architecture July 2005 Part number S51002-3.2 Chapter Configuration & Testing July 2005 Part number S51003-1.3 Chapter DC & Switching Characteristics January 2006 Part number S51004-3.4 Chapter Reference & Ordering Information September 2004 Part number S51005-2.1 Altera Corporation Stratix Device Handbook, Volume 1 viii Altera Corporation About This Handbook This handbook provides comprehensive information about the Stratix family of devices. How to Find Information You can find more information in the following ways: • The Adobe Acrobat Find feature, which searches the text of a PDF document. Click the binoculars toolbar icon to open the Find dialog box. • Acrobat bookmarks, which serve as an additional table of contents in PDF documents. • Thumbnail icons, which provide miniature previews of each page, provide a link to the pages. • Numerous links, shown in green text, which allow you to jump to related information. How to Contact Altera For the most up-to-date information about Altera products, go to the Altera world-wide web site at For technical support on this product, go to For additional information about Altera products, consult the sources shown below. Information Type Technical support Product literature Altera literature services Non-technical customer service site USA & Canada 800-EPLD 3753 7:00 a.m. to 5:00 p.m. Pacific Time 800 767-3753 All Other Locations +1 408-544-8767 7:00 a.m. to 5:00 p.m. GMT -8:00 Pacific Time + 1 408-544-7000 7:00 a.m. to 5:00 p.m. GMT -8:00 Pacific Time Altera Corporation Typographic Conventions Stratix Device Handbook, Volume 1 Typographic Conventions This document uses the typographic conventions shown below. Visual Cue Meaning Bold Type with Initial Capital Letters Command names, dialog box titles, checkbox options, and dialog box options are shown in bold, initial capital letters. Example Save As dialog box. bold type External timing parameters, directory names, project names, disk drive names, filenames, filename extensions, and software utility names are shown in bold type. Examples fMAX, directory, d drive, chiptrip.gdf file. Italic Type with Initial Capital Document titles are shown in italic type with initial capital letters. Example AN 75: Letters High-Speed Board Designs. Italic type This section provides the data sheet specifications for devices. They contain feature definitions of the internal architecture, configuration and JTAG boundary-scan testing information, DC operating conditions, AC timing parameters, a reference to power consumption, and ordering information for Stratix devices. This section contains the following chapters: • Chapter 1, Introduction • Chapter 2, Stratix Architecture • Chapter 3, Configuration & Testing • Chapter 4, DC & Switching Characteristics • Chapter 5, Reference & Ordering Information Date/Version Changes Made July 2005, v3.2 ● Minor content changes. September 2004, v3.1 ● Updated Table on page April 2004, v3.0 ● Main section page numbers changed on first page. ● Changed PCI-X to PCI-X in “Features” on page ● Global change from SignalTap to SignalTap II. ● The DSP blocks in “Features” on page provide dedicated implementation of multipliers that are now “faster than 300 MHz.” January 2004, v2.2 ● Updated -5 speed grade device information in Table October 2003, v2.1 ● Add -8 speed grade device information. July 2003, v2.0 ● Format changes throughout chapter. Altera Corporation Section Stratix Device Family Data Sheet Stratix Device Handbook, Volume 1 Date/Version Changes Made July 2005 v3.2 ● Added “Clear Signals” section. ● Updated “Power Sequencing & Hot Socketing” section. ● Format changes. September 2004, v3.1 ● Updated fast regional clock networks description on page ● Deleted the word preliminary from the “specification for the maximum time to relock is 100 µs” on page ● Added information about differential SSTL and HSTL outputs in “External Clock Outputs” on page ● Updated notes in Figure on page ● Added information about m counter to “Clock Multiplication & Division” on page ● Updated Note 1 in Table on page ● Updated description of “Clock Multiplication & Division” on page ● Updated Table on page ● Added references to AN 349 and AN 329 to “External RAM Interfacing” on page ● Table on page updated the table, updated Notes 3 and Notes 4, 5, and 6, are now Notes 5, 6, and 7, respectively. ● Updated Table on page ● Added information about PCI Compliance to page ● Table on page updated the table and deleted Note ● Updated reference to device pin-outs now being available on the web on page ● Added Notes 4 and 5 to Table on page ● Updated Note 3 in Table on page ● Updated Note 5 in Table on page April 2004, v3.0 ● Added note 3 to rows 11 and 12 in Table ● Deleted “Stratix and Stratix GX Device PLL Availability” table. ● Added I/O standards row in Table that support max and min strength. ● Row clk [1,3,8,10] was removed from Table ● Added checkmarks in Enhanced column for LVPECL, 3.3-V PCML, LVDS, and HyperTransport technology rows in Table ● Removed the Left and Right I/O Banks row in Table ● Changed RCLK values in Figures and ● External RAM Interfacing section replaced. November 2003, v2.2 ● Added 672-pin BGA package information in Table ● Removed support for series and parallel on-chip termination. ● Termination Technology renamed differential on-chip termination. ● Updated the number of channels per PLL in Tables 2-38 through 2- ● Updated Figures and October 2003, v2.1 ● Updated DDR I information. ● Updated Table ● Added Tables and ● Updated Figures and ● Updated the Lock Detect section. Section Altera Corporation Stratix Device Family Data Sheet Date/Version Changes Made July 2003, v2.0 ● Added reference on page 2-73 to Figures 2-50 and 2-51 for RCLK connections. ● Updated ranges for EPLL post-scale and pre-scale dividers on page ● Updated PLL Reconfiguration frequency from 25 to 22 MHz on page ● New requirement to assert are set signal each PLL when it has to reacquire lock on either a new clock after loss of lock page ● Updated max input frequency for CLK[1,3,8,10] from 462 to 500, Table Software. Device Pin-Outs Ordering Information Altera Corporation July 2005 The Stratix family offers the following features: • 10,570 to 79,040 LEs see Table • Up to 7,427,520 RAM bits 928,440 bytes available without reducing logic resources • TriMatrixTM memory consisting of three RAM block sizes to implement true dual-port memory and first-in first-out FIFO buffers • High-speed DSP blocks provide dedicated implementation of multipliers faster than 300 MHz , multiply-accumulate functions, and finite impulse response FIR filters • Up to 16 global clocks with 22 clocking resources per device region • Up to 12 PLLs four enhanced PLLs and eight fast PLLs per device provide spread spectrum, programmable bandwidth, clock switchover, real-time PLL reconfiguration, and advanced multiplication and phase shifting • Support for numerous single-ended and differential I/O standards • High-speed differential I/O support on up to 116 channels with up to 80 channels optimized for 840 megabits per second Mbps • Support for high-speed networking and communications bus standards including RapidIO, UTOPIA IV, CSIX, HyperTransportTM technology, 10G Ethernet XSBI, SPI-4 Phase 2 POS-PHY Level 4 , and SFI-4 • Differential on-chip termination support for LVDS • Support for high-speed external memory, including zero bus turnaround ZBT SRAM, quad data rate QDR and QDRII SRAM, double data rate DDR SDRAM, DDR fast cycle RAM FCRAM , and single data rate SDR SDRAM • Support for 66-MHz PCI 64 and 32 bit in -6 and faster speed-grade devices, support for 33-MHz PCI 64 and 32 bit in -8 and faster speed-grade devices • Support for 133-MHz PCI-X in -5 speed-grade devices • Support for 100-MHz PCI-X in -6 and faster speed-grade devices • Support for 66-MHz PCI-X in -7 speed-grade devices • Support for multiple intellectual property megafunctions from Altera functions and Altera Megafunction Partners Program AMPPSM megafunctions • Support for remote configuration updates Stratix Device Handbook, Volume 1 Altera Corporation July 2005 Introduction Table Stratix Device Features EP1S10, EP1S20, EP1S25, EP1S30 LEs M512 RAM blocks 32 x 18 bits M4K RAM blocks 128 x 36 bits M-RAM blocks 4K x 144 bits Total RAM bits DSP blocks Embedded multipliers 1 PLLs Maximum user I/O pins EP1S10 10,570 94 60 1 920,448 6 48 6 EP1S20 18,460 194 82 2 1,669,248 10 80 6 586 EP1S25 25,660 224 138 2 1,944,576 10 80 6 706 EP1S30 32,470 295 171 4 3,317,184 12 96 10 726 Table Stratix Device Features EP1S40, EP1S60, EP1S80 LEs M512 RAM blocks 32 x 18 bits M4K RAM blocks 128 x 36 bits M-RAM blocks 4K x 144 bits Total RAM bits DSP blocks Embedded multipliers 1 PLLs Maximum user I/O pins EP1S40 41,250 384 183 4 3,423,744 14 112 12 822 EP1S60 57,120 574 292 6 5,215,104 18 144 12 1,022 EP1S80 79,040 767 364 9 7,427,520 22 176 12 1,238 Note to Tables and 1 This parameter lists the total number of 9 x 9-bit multipliers for each device. For the total number of 18 x 18-bit multipliers per device, divide the total number of 9 x 9-bit multipliers by For the total number of 36 x 36-bit multipliers per device, divide the total number of 9 x 9-bit multipliers by Altera Corporation July 2005 Stratix Device Handbook, Volume 1 Reference & Ordering Information S51005-2.1 Software devices are supported by the II design software, which provides a comprehensive environment for system-on-aprogrammable-chip SOPC design. The Quartus II software includes HDL and schematic design entry, compilation and logic synthesis, full simulation and advanced timing analysis, II logic analyzer, and device configuration. See the Design Software Selector Guide for more details on the Quartus II software features. The Quartus II software supports the Windows XP/2000/NT/98, Sun Solaris, Linux Red Hat v7.1 and HP-UX operating systems. It also supports seamless integration with industry-leading EDA tools through the interface. Device Pin-Outs Stratix device pin-outs can be found on the Altera web site Ordering Information Figure describes the ordering codes for Stratix devices. For more information on a specific package, see the Package Information for Stratix Devices chapter. Altera Corporation September 2004 Ordering Information Figure Stratix Device Packaging Ordering Information Family Signature EP1S Stratix Device Type 10 20 25 30 40 60 80 Package Type B Ball-grid array BGA F FineLine BGA EP1S 1508 ES Optional Suffix Indicates specific device options or shipment method. ES Engineering sample Speed Grade 5, 6, or 7, with 5 being the fastest Operating Temperature C Commercial temperature tJ = C to C I Industrial temperature tJ = C to C Pin Count Number of pins for a particular BGA or FineLine BGA package Stratix Device Handbook, Volume 1 Altera Corporation September 2004 Index Accumulator Adder/Output Blocks Adder/Subtractor Accumulator AGP 1x Specifications AGP 2x Specifications Architecture 36 x 36 Multiply Mode addnsub Signal Block Diagram Bus Hold Byte Alignment Carry-Select Chain Clear & Preset Logic Control Combined Resources Dedicated Circuitry Device Resources Device Routing Scheme Digital Signal Processing Block Direct Link Connection Dynamic Arithmetic Mode in LE Four-Multipliers Adder Mode Functional Description LAB Interconnects Logic Array Blocks Structure LE Operating Modes Logic Elements Modes of Operation Multiplier Size & Configurations per DSP block Multiply-Accumulator Mode MultiTrack Interconnect Normal Mode in LE Open-Drain Output Power Sequencing & Hot Socketing Programmable Drive Strength Programmable Pull-Up Resistor Simple Multiplier Mode Single-Port Mode Slew-Rate Control Two-Multipliers Adder Mode Adder Mode Implementing Complex Multiply Class I Specifications Class II Specifications Clocks Clock Feedback Clock Multiplication & Division Clock Switchover Delay EP1S10, EP1S20 & EP1S25 Device I/O Clock Groups EP1S25, EP1S20 & EP1S10 Device Fast Clock Pin Connections to Fast Regional Clocks EP1S30 Device Fast Regional Clock Pin Connections to Fast Regional Clocks EP1S30, EP1S40, EP1S60, EP1S80 Device I/O Clock Groups External Clock Inputs Outputs for Enhanced PLLs 11 & 12 Outputs for PLLs 5 & 6 Fast Regional Clock External I/O Timing Parameters Fast Regional Clock Network Altera Corporation Stratix Device Handbook, Volume 1 Global & Hierarchical Clocking Global & Regional Clock Connections from Side Pins & Fast PLL Outputs from Top Clock Pins & Enhanced PLL Ordering Information Device Pin-Outs Packaging Ordering Information Reference & Ordering Information Output Registers Output Selection Multiplexer Packaging BGA Package Sizes Device Speed Grades FineLine BGA Package Sizes PCI-X Specifications Phase Shifting PLL Advanced Clear & Enable Control Dynamically Programmable Counters & De- lays in Stratix Device Enhanced PLLs Enhanced Fast PLLs Fast PLL Channel Layout EP1S10, EP1S20 or EP1S25 Devices Channel Layout EP1S30 to EP1S80 Devices Port I/O Standards I/O Standards Supported for Enhanced PLL Pins Lock Detect & Programmable Gated Locked PLL Locations Programmable Bandwidth Programmable Delay Chain Programmable Duty Cycle Reconfiguration Testing Temperature Sensing Diode Electrical Characteristics External Temperature vs. Temperature-Sensing Diode Voltage Timing DSP Block Internal Timing Microparameter Descriptions Microparameters Dual-Port RAM Timing Microparameter Waveform External Timing in Stratix Devices High-Speed I/O Timing High-Speed Timing Specifications & Terminology Internal Parameters IOE Internal Timing Microparameter Descriptions LE Internal Timing Microparameters Logic Elements Internal Timing Microparameter Descriptions Model PLL Timing Preliminary & Final Stratix Device Timing Model Status Stratix JTAG Timing Parameters & Values TriMatrix Memory TriMatrix Memory Features Altera Corporation

PDF Datasheet Preview

Stratix Device Handbook, Volume 1
101 Innovation Drive San Jose, CA 95134 408 544-7000

S5V1-3.4

Copyright 2006 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

Altera Corporation

Contents

About This Handbook ix

How to Find Information ix How to Contact Altera ix Typographic Conventions x

Section I. Stratix Device Family Data Sheet

Chapter Introduction

Introduction Features

Chapter Stratix Architecture

Functional Description Logic Array Blocks

LAB Interconnects LAB Control Signals Logic Elements LUT Chain & Register Chain addnsub Signal LE Operating Modes Clear & Preset Logic Control MultiTrack Interconnect TriMatrix Memory Modes Clear Signals Parity Bit Support Shift Register Support Memory Block Size Independent Clock Mode Input/Output Clock Mode Read/Write Clock Mode Single-Port Mode Multiplier Block Adder/Output Blocks Modes of Operation

Altera Corporation

Contents

Stratix Device Handbook, Volume 1

DSP Block Interface PLLs & Clock Networks

Global & Hierarchical Clocking Enhanced & Fast PLLs Enhanced PLLs Fast PLLs I/O Structure Double-Data Rate I/O Pins External RAM Interfacing Programmable Drive Strength Open-Drain Output Slew-Rate Control Bus Hold Programmable Pull-Up Resistor Advanced I/O Standard Support Differential On-Chip Termination MultiVolt I/O Interface High-Speed Differential I/O Support Dedicated Circuitry Byte Alignment Power Sequencing & Hot Socketing

Chapter Configuration & Testing

IEEE Std. JTAG Boundary-Scan Support SignalTap II Embedded Logic Analyzer Configuration

Operating Modes Configuring Stratix FPGAs with JRunner Configuration Schemes Partial Reconfiguration Remote Update Configuration Modes Stratix Automated Single Event Upset SEU Detection Custom-Built Circuitry Software Interface Temperature Sensing Diode

Chapter DC & Switching Characteristics

Operating Conditions Power Consumption Timing Model

Preliminary & Final Timing Performance Internal Timing Parameters External Timing Parameters Stratix External I/O Timing I/O Timing Measurement Methodology External I/O Delay Parameters

Altera Corporation

Contents

Contents

Maximum Input & Output Clock Rates High-Speed I/O Specification PLL Specifications DLL Specifications
Chapter Reference & Ordering Information
Software Device Pin-Outs Ordering Information

Index

Altera Corporation

Contents

Stratix Device Handbook, Volume 1

Altera Corporation

Chapter Introduction

July 2005

Part number S51001-3.2

Chapter Stratix Architecture

July 2005

Part number S51002-3.2

Chapter Configuration & Testing

July 2005

Part number S51003-1.3

Chapter DC & Switching Characteristics

January 2006

Part number S51004-3.4
Chapter Reference & Ordering Information

September 2004

Part number S51005-2.1

Altera Corporation

Stratix Device Handbook, Volume 1
viii

Altera Corporation

About This Handbook

This handbook provides comprehensive information about the Stratix family of devices.

How to Find Information

You can find more information in the following ways:
• The Adobe Acrobat Find feature, which searches the text of a PDF document. Click the binoculars toolbar icon to open the Find dialog box.
• Acrobat bookmarks, which serve as an additional table of contents in PDF documents.
• Thumbnail icons, which provide miniature previews of each page, provide a link to the pages.
• Numerous links, shown in green text, which allow you to jump to related information.

How to Contact Altera

For the most up-to-date information about Altera products, go to the Altera world-wide web site at For technical support on this product, go to For additional information about Altera products, consult the sources shown below.

Information Type

Technical support

Product literature Altera literature services Non-technical customer service site

USA & Canada
800-EPLD 3753 7:00 a.m. to 5:00 p.m. Pacific Time
800 767-3753

All Other Locations
+1 408-544-8767 7:00 a.m. to 5:00 p.m. GMT -8:00 Pacific Time
+ 1 408-544-7000 7:00 a.m. to 5:00 p.m. GMT -8:00 Pacific Time

Altera Corporation

Typographic Conventions

Stratix Device Handbook, Volume 1

Typographic Conventions

This document uses the typographic conventions shown below.

Visual Cue

Meaning

Bold Type with Initial Capital Letters

Command names, dialog box titles, checkbox options, and dialog box options are shown in bold, initial capital letters. Example Save As dialog box.
bold type

External timing parameters, directory names, project names, disk drive names, filenames, filename extensions, and software utility names are shown in bold type. Examples fMAX, directory, d drive, chiptrip.gdf file.

Italic Type with Initial Capital Document titles are shown in italic type with initial capital letters. Example AN 75:

Letters

High-Speed Board Designs.

Italic type
This section provides the data sheet specifications for devices. They contain feature definitions of the internal architecture, configuration and JTAG boundary-scan testing information, DC operating conditions, AC timing parameters, a reference to power consumption, and ordering information for Stratix devices.

This section contains the following chapters:
• Chapter 1, Introduction
• Chapter 2, Stratix Architecture
• Chapter 3, Configuration & Testing
• Chapter 4, DC & Switching Characteristics
• Chapter 5, Reference & Ordering Information

Date/Version

Changes Made

July 2005, v3.2
● Minor content changes.

September 2004, v3.1 ● Updated Table on page

April 2004, v3.0
● Main section page numbers changed on first page. ● Changed PCI-X to PCI-X in “Features” on page ● Global change from SignalTap to SignalTap II. ● The DSP blocks in “Features” on page provide dedicated
implementation of multipliers that are now “faster than 300 MHz.”

January 2004, v2.2 ● Updated -5 speed grade device information in Table

October 2003, v2.1 ● Add -8 speed grade device information.

July 2003, v2.0 ● Format changes throughout chapter.

Altera Corporation

Section

Stratix Device Family Data Sheet

Stratix Device Handbook, Volume 1

Date/Version

Changes Made

July 2005 v3.2
● Added “Clear Signals” section. ● Updated “Power Sequencing & Hot Socketing” section. ● Format changes.

September 2004, v3.1 ● Updated fast regional clock networks description on page ● Deleted the word preliminary from the “specification for the maximum time to relock is 100 µs” on page ● Added information about differential SSTL and HSTL outputs in “External Clock Outputs” on page ● Updated notes in Figure on page ● Added information about m counter to “Clock Multiplication & Division” on page ● Updated Note 1 in Table on page ● Updated description of “Clock Multiplication & Division” on page ● Updated Table on page ● Added references to AN 349 and AN 329 to “External RAM Interfacing” on page ● Table on page updated the table, updated Notes 3 and Notes 4, 5, and 6, are now Notes 5, 6, and 7, respectively. ● Updated Table on page ● Added information about PCI Compliance to page ● Table on page updated the table and deleted Note ● Updated reference to device pin-outs now being available on the web on page ● Added Notes 4 and 5 to Table on page ● Updated Note 3 in Table on page ● Updated Note 5 in Table on page

April 2004, v3.0
● Added note 3 to rows 11 and 12 in Table ● Deleted “Stratix and Stratix GX Device PLL Availability” table. ● Added I/O standards row in Table that support max and min
strength. ● Row clk [1,3,8,10] was removed from Table ● Added checkmarks in Enhanced column for LVPECL, 3.3-V PCML,

LVDS, and HyperTransport technology rows in Table ● Removed the Left and Right I/O Banks row in Table ● Changed RCLK values in Figures and ● External RAM Interfacing section replaced.

November 2003, v2.2
● Added 672-pin BGA package information in Table ● Removed support for series and parallel on-chip termination. ● Termination Technology renamed differential on-chip termination. ● Updated the number of channels per PLL in Tables 2-38 through 2-
● Updated Figures and

October 2003, v2.1
● Updated DDR I information. ● Updated Table ● Added Tables and ● Updated Figures and ● Updated the Lock Detect section.

Section

Altera Corporation

Stratix Device Family Data Sheet

Date/Version

Changes Made

July 2003, v2.0
● Added reference on page 2-73 to Figures 2-50 and 2-51 for RCLK connections.
● Updated ranges for EPLL post-scale and pre-scale dividers on page
● Updated PLL Reconfiguration frequency from 25 to 22 MHz on page
● New requirement to assert are set signal each PLL when it has to reacquire lock on either a new clock after loss of lock page
● Updated max input frequency for CLK[1,3,8,10] from 462 to 500, Table
Software. Device Pin-Outs Ordering Information

Altera Corporation

July 2005

The Stratix family offers the following features:
• 10,570 to 79,040 LEs see Table
• Up to 7,427,520 RAM bits 928,440 bytes available without reducing
logic resources
• TriMatrixTM memory consisting of three RAM block sizes to
implement true dual-port memory and first-in first-out FIFO buffers
• High-speed DSP blocks provide dedicated implementation of multipliers faster than 300 MHz , multiply-accumulate functions, and finite impulse response FIR filters
• Up to 16 global clocks with 22 clocking resources per device region
• Up to 12 PLLs four enhanced PLLs and eight fast PLLs per device provide spread spectrum, programmable bandwidth, clock switchover, real-time PLL reconfiguration, and advanced multiplication and phase shifting
• Support for numerous single-ended and differential I/O standards
• High-speed differential I/O support on up to 116 channels with up to 80 channels optimized for 840 megabits per second Mbps
• Support for high-speed networking and communications bus standards including RapidIO, UTOPIA IV, CSIX, HyperTransportTM technology, 10G Ethernet XSBI, SPI-4 Phase 2 POS-PHY Level 4 , and SFI-4
• Differential on-chip termination support for LVDS
• Support for high-speed external memory, including zero bus turnaround ZBT SRAM, quad data rate QDR and QDRII SRAM, double data rate DDR SDRAM, DDR fast cycle RAM FCRAM , and single data rate SDR SDRAM
• Support for 66-MHz PCI 64 and 32 bit in -6 and faster speed-grade devices, support for 33-MHz PCI 64 and 32 bit in -8 and faster speed-grade devices
• Support for 133-MHz PCI-X in -5 speed-grade devices
• Support for 100-MHz PCI-X in -6 and faster speed-grade devices
• Support for 66-MHz PCI-X in -7 speed-grade devices
• Support for multiple intellectual property megafunctions from Altera functions and Altera Megafunction Partners Program AMPPSM megafunctions
• Support for remote configuration updates

Stratix Device Handbook, Volume 1

Altera Corporation July 2005

Introduction

Table Stratix Device Features EP1S10, EP1S20, EP1S25, EP1S30

LEs M512 RAM blocks 32 x 18 bits M4K RAM blocks 128 x 36 bits M-RAM blocks 4K x 144 bits Total RAM bits DSP blocks Embedded multipliers 1 PLLs Maximum user I/O pins

EP1S10
10,570 94 60 1
920,448 6 48 6

EP1S20
18,460 194 82 2
1,669,248 10 80 6 586

EP1S25
25,660 224 138 2
1,944,576 10 80 6 706

EP1S30
32,470 295 171 4
3,317,184 12 96 10 726

Table Stratix Device Features EP1S40, EP1S60, EP1S80

LEs M512 RAM blocks 32 x 18 bits M4K RAM blocks 128 x 36 bits M-RAM blocks 4K x 144 bits Total RAM bits DSP blocks Embedded multipliers 1 PLLs Maximum user I/O pins

EP1S40
41,250 384 183 4
3,423,744 14 112 12 822

EP1S60
57,120 574 292 6
5,215,104 18 144 12
1,022

EP1S80
79,040 767 364 9
7,427,520 22 176 12
1,238

Note to Tables and 1 This parameter lists the total number of 9 x 9-bit multipliers for each device. For the total number of 18 x 18-bit
multipliers per device, divide the total number of 9 x 9-bit multipliers by For the total number of 36 x 36-bit multipliers per device, divide the total number of 9 x 9-bit multipliers by

Altera Corporation July 2005

Stratix Device Handbook, Volume 1
Reference & Ordering Information

S51005-2.1

Software
devices are supported by the II design software, which provides a comprehensive environment for system-on-aprogrammable-chip SOPC design. The Quartus II software includes HDL and schematic design entry, compilation and logic synthesis, full simulation and advanced timing analysis, II logic analyzer, and device configuration. See the Design Software Selector Guide for more details on the Quartus II software features.

The Quartus II software supports the Windows XP/2000/NT/98, Sun Solaris, Linux Red Hat v7.1 and HP-UX operating systems. It also supports seamless integration with industry-leading EDA tools through the interface.

Device Pin-Outs Stratix device pin-outs can be found on the Altera web site
Ordering Information
Figure describes the ordering codes for Stratix devices. For more information on a specific package, see the Package Information for Stratix Devices chapter.

Altera Corporation

September 2004
Ordering Information
Figure Stratix Device Packaging Ordering Information

Family Signature

EP1S Stratix

Device Type 10 20 25 30 40 60 80

Package Type B Ball-grid array BGA F FineLine BGA

EP1S
1508

ES Optional Suffix

Indicates specific device options or shipment method. ES Engineering sample

Speed Grade 5, 6, or 7, with 5 being the fastest

Operating Temperature C Commercial temperature tJ = C to C I Industrial temperature tJ = C to C

Pin Count Number of pins for a particular BGA or FineLine BGA package

Stratix Device Handbook, Volume 1

Altera Corporation September 2004

Index

Accumulator Adder/Output Blocks Adder/Subtractor

Accumulator

AGP 1x Specifications AGP 2x Specifications Architecture
36 x 36 Multiply Mode addnsub Signal Block Diagram Bus Hold Byte Alignment Carry-Select Chain Clear & Preset Logic Control Combined Resources Dedicated Circuitry Device Resources Device Routing Scheme Digital Signal Processing Block Direct Link Connection Dynamic Arithmetic Mode
in LE Four-Multipliers

Adder Mode Functional Description LAB

Interconnects Logic Array Blocks Structure LE Operating Modes Logic Elements Modes of Operation Multiplier Size & Configurations per DSP
block Multiply-Accumulator Mode MultiTrack Interconnect Normal Mode
in LE

Open-Drain Output Power Sequencing & Hot Socketing Programmable Drive Strength Programmable Pull-Up Resistor Simple Multiplier Mode Single-Port Mode Slew-Rate Control Two-Multipliers

Adder Mode Adder Mode Implementing Complex

Multiply

Class I Specifications Class II Specifications Clocks

Clock Feedback Clock Multiplication & Division Clock Switchover

Delay EP1S10, EP1S20 & EP1S25

Device I/O Clock Groups

EP1S25, EP1S20 & EP1S10 Device Fast Clock Pin Connections to Fast Regional Clocks

EP1S30 Device Fast Regional Clock Pin Connections to Fast Regional Clocks

EP1S30, EP1S40, EP1S60, EP1S80 Device I/O Clock Groups

External Clock Inputs Outputs for Enhanced PLLs 11 & 12 Outputs for PLLs 5 & 6

Fast Regional Clock External I/O Timing Parameters

Fast Regional Clock Network

Altera Corporation

Stratix Device Handbook, Volume 1

Global & Hierarchical Clocking Global & Regional Clock Connections
from Side Pins & Fast PLL Outputs from Top Clock Pins & Enhanced PLL
Ordering Information Device Pin-Outs Packaging Ordering Information Reference & Ordering Information

Output Registers Output Selection Multiplexer

Packaging BGA Package Sizes Device Speed Grades FineLine BGA Package Sizes

PCI-X Specifications Phase Shifting PLL

Advanced Clear & Enable Control Dynamically Programmable Counters & De-
lays in Stratix Device Enhanced PLLs Enhanced Fast PLLs Fast PLL Channel Layout EP1S10, EP1S20 or

EP1S25 Devices Channel Layout EP1S30 to EP1S80

Devices

Port I/O Standards I/O Standards Supported for Enhanced PLL

Pins Lock Detect & Programmable Gated

Locked PLL Locations Programmable Bandwidth Programmable Delay Chain Programmable Duty Cycle Reconfiguration

Testing Temperature Sensing Diode Electrical Characteristics External Temperature vs. Temperature-Sensing Diode Voltage

Timing DSP Block Internal Timing Microparameter Descriptions Microparameters Dual-Port RAM Timing Microparameter Waveform External Timing in Stratix Devices High-Speed I/O Timing High-Speed Timing Specifications & Terminology Internal Parameters IOE Internal Timing Microparameter Descriptions LE Internal Timing Microparameters Logic Elements Internal Timing Microparameter Descriptions Model PLL Timing Preliminary & Final Stratix Device Timing Model Status Stratix JTAG Timing Parameters & Values

TriMatrix Memory TriMatrix Memory Features

Altera Corporation

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived EP1S10B672I7 Datasheet file may be downloaded here without warranties.

Datasheet ID: EP1S10B672I7 517157