PLMT3000-100NC

PLMT3000-100NC Datasheet


PLMJ1213 PLMT1064

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New& sViews SecondQuarter, May2000 Newsletter for Altera Customers

Altera Announces the Nios Processor for Embedded Systems Development

Altera is a leader in providing the key elements required for successful system-on-aprogrammable-chip SOPC designs, including high performance, full-featured devices, integrated development tools, and a comprehensive portfolio of intellectual property IP . Recognizing the importance of microprocessors in SOC designs, Altera has established itself as the preeminent source of processor IP through strong partnerships with industry leaders. Altera now enhances this processor IP selection with ExcaliburTM embedded processor programmable logic device PLD solutions. Consisting of both hard and soft core technologies that integrate RISC processors into PLDs, the Excalibur embedded processor solutions offer the widest range of capabilities and the high performance of dedicated hardware implementation. With the introduction of the Excalibur embedded processor PLD solutions, designers can reap all the benefits of SOPC design.

Advantages of SOPC

The strengths of SOC design include higher integration and increased system performance. SOPC designs add additional benefits such as programmability and fast time-to-market, with the flexibility of PLDs. With these programmable devices, a designer can implement several different iterations of a system in hardware in a fraction of the time required to implement a custom component version. This flexibility allows designers to not only develop a product in a shorter amount of
time, but to explore different system architectures and feature sets to deliver the best possible combination in their product. By fully integrating the processor into the PLD design flow, the Excalibur solutions give system designers unprecedented freedom to determine which functions should be executed in software and which would benefit the most from dedicated hardware implementation.

Excalibur Solutions

The Altera Excalibur solutions consist of the following families:
s The NiosTM family of soft core embedded configurable 16- or 32-bit embedded RISC processor
s The embedded processor ARM9 embedded processor core with 32-bit architecture and a 32-bit RISC engine
s The embedded processor MIPS 4KcTM embedded processor core with 32-bit architecture and R4000TM TLB and privileged-mode extensions.

The first Excalibur embedded processor PLD solution is the Nios family, a 16- or 32-bit embedded RISC soft core processor that is easily configured to meet several different demands, and rapidly integrated into any Altera-based design. Although the Nios embedded processors are initially optimized for APEXTM devices, they
continued on page 4

May 2000 M-NV-Q200-01

News & Views Altera Corporation

The Programmable Solutions

Introducing the Excalibur Development Kit

Featuring Nios

The Development Kit that Gets You on the Cutting Edge The Nios soft core embedded processor, the first of Altera’s new Excalibur embedded processor solutions to ship, delivers just what you need to create system-on-aprogrammable-chip SOPC designs.

This new flexible embedded processor solution offers a 32-bit configuration, up to 50 MIPS performance, and an equivalent volume price point of The development kit is available now with everything you need to get started.

A Complete Solution for Only This Excalibur Development Kit contains:
s Nios Configurable RISC Embedded Processor Core and Peripherals
s Quartus Programmable Logic Development Software s C/C++ Compiler and Debugger from
a Red Company s ByteBlasterMV Download Cable s Development Board Including an APEX EP20K200E

Device s Reference Design and Documentation

Free Hands-on Workshops Intensive three-hour workshops, starting in June, will teach you how to create an SOPC design using the Nios soft core embedded processor in an APEX device. You will develop and compile C code, then execute and troubleshoot it on the development board. You will also learn about the GNUPro Compiler and Debugger from Cygnus, a Red Hat company, included in the Excalibur Development Kit.

Win a Free Excalibur Development Kit! Each workshop will feature a drawing for a free Excalibur Development Kit. You must be present to win, so sign up today.

Copyright 2000 Altera Corporation. Altera, APEX, APEX 20K, APEX 20KE, ByteBlasterMV, Excalibur, Nios, Quartus, and specific designations are trademarks and/or service marks of Altera Corporation in the United States and other countries. Other brands or products are trademarks of their respective holders. The specifications contained herein are subject to change without notice. All rights reserved.

Table ofContents

Features Altera Announces the Nios Processor for

Embedded Systems Development 1 Design Tips Improving Quartus

Design Performance 14 Customer Application Bridging the Gap:
dataBlizzard & Reliaspan 18

Altera News Altera & Red Hat Form Partnership to Provide

Development Software for Nios 6 Sign Up Now for Free Excalibur Workshops 17 ACEX Devices Address Communications Market

Need for Low-Cost Programmable Logic 24 Altera's New SignalTap Plus System Analyzer

Provides Simultaneous On-Chip & Off-Chip Debug Capabilities 26 DCM Technologies' CoreX-V10 Increased Performance Produces Faster Megafunctions 28 True-LVDS Solution Provides 840-Mbps Data Transfer Rates 30 Altera's Turbo Encoder & Decoder Push the Technology Envelope for High-Speed 3G Wireless Applications 32

Devices & Tools Eight APEX 20KE Devices Now Shipping 7 True-LVDS Support in APEX 20KE Devices 7 5.0-V Tolerant APEX 20K & APEX 20KE Devices 7 APEX 20K Product Transition 8 ACEX 1K Devices Shipping Now................................ 8 ACEX 2K Devices Coming Soon 8 All FLEX 10KE Devices Available 8

FLEX 10K Product Transitions 8 FLEX 10KE Industrial-Temperature Devices 9 MAX 7000A Devices 10 MAX 7000B Devices Support Advanced

I/O Standards 10 MAX 7000S Family 11 MAX 3000A Devices 11 4-Mbit Configuration Device Coming Soon 11 Quartus Software Version

Available Now 11 Quartus Operating System Update 11 MAX+PLUS II Software Version Now
10KE devices are offered with the PLL feature in -1 and -2 speed grades to reduce clock skew and allow clock multiplication. These devices have an “X” suffix in the ordering code e.g., EPF10K100EQC208-1X . To assist designers in implementing their projects in FLEX 10KE devices, the MAX+PLUS II software offers design support for all device package options. Table 3 shows all of the 2.5-V 10KE device packages and speed grades.

FLEX 10K Product Transitions
2.5-V EPF10K50E and EPF10K200E devices have migrated from a 0.25-µm process to a 0.22-µm process. All other members of the FLEX 10KE family are already manufactured on a 0.22-µm process. EPF10K50V devices are migrating from a 0.30-µm, 3-layer-metal

Altera Corporation News & Views

May 2000

Devices & Tools

Table FLEX 10KE Devices

Table FLEX 10K Device Migration

Device

Offerings

EPF10K30E
144-pin TQFP 208-pin PQFP 256-pin FineLine BGA 484-pin FineLine BGA PLL all packages

EPF10K50S
144-pin TQFP 208-pin PQFP 240-pin PQFP 256-pin FineLine BGA 356-pin BGA 484-pin FineLine BGA PLL all packages

EPF10K100E 208-pin PQFP 240-pin PQFP 256-pin FineLine BGA 356-pin BGA 484-pin FineLine BGA PLL all packages

EPF10K130E 240-pin PQFP 356-pin BGA 484-pin FineLine BGA 600-pin BGA 672-pin FineLine BGA PLL all packages

EPF10K200S 240-pin RQFP 356-pin BGA 484-pin FineLine BGA 600-pin BGA 672-pin FineLine BGA PLL all packages

Speed Grade
-1, -2, -3 -1, -2, -3 -1, -2, -3 -1, -2, -3 -1X, -2X
-1, -2, -3 -1, -2, -3 -1, -2, -3 -1, -2, -3 -1, -2, -3 -1, -2, -3 -1X, -2X
-1, -2, -3 -1, -2, -3 -1, -2, -3 -1, -2, -3 -1, -2, -3 -1X, -2X
-1, -2, -3 -1, -2, -3 -1, -2, -3 -1, -2, -3 -1, -2, -3 -1X, -2X
-1, -2, -3 -1, -2, -3 -1, -2, -3 -1, -2, -3 -1, -2, -3 -1X, -2X
process to a 0.30-µm, 4-layer-metal process in September Table 4 outlines the process migration schedule and lists the reference documentation associated with this migration. You can download these documents from the Customer Notifications page on the Altera web site at

FLEX 10KE Industrial-Temperature Devices

All FLEX 10KE devices are now available in industrial-temperature grades. Table 5 lists the industrial-temperature FLEX 10KE devices.

Device Core Date Reference Process

Voltage

EPF10K10A

Done PCN 9810

EPF10K30A

Done PCN 9810

EPF10K50V

Done PCN 9810 1

Sept. 2000

PCN 9915 2

EPF10K100A Done PCN 9810

EPF10K10

Done

PCN 9901 ADV 9909

EPF10K20
For a limited time, all Altera customers with current subscriptions will receive a 10% discount off of the renewal subscription list price as long as the renewal subscription is ordered before their current subscription expires. This offer is valid to all customers on active subscription. The renewal ordering code can be used to renew FIXEDPC, FLOATPC, or FLOATNET subscriptions.

The 10% discount applies to orders received on or before the subscription expiration date. A renewal subscription extends the subscription by 12 months from the existing expiration date. Customers do not lose any months on their existing subscription by renewing early.

You will receive updates for both the Quartus and MAX+PLUS II software for an additional 12 months after your current subscription was set to expire. You also receive world-class synthesis and simulation software with the renewal of your subscription. For synthesis, Synopsys FPGA Express-Altera and Exemplar Logic LeonardoSpectrum-Altera is included with your renewal. You will also receive Model Technology ModelSim-Altera for behavioral HDL simulation and test bench support. By renewing a subscription before it expires, you are guaranteed to receive the latest version of the Quartus and MAX+PLUS II software without interruption and gain access to world class synthesis and simulation software.

License Files for OEM World-Class Synthesis & Simulation Tools Available Today

Altera has entered into OEM agreements with Synopsys and Mentor Graphics to provide Altera customers with world-class synthesis and simulation products. Altera is shipping the Synopsys FPGA Express version and Exemplar Logic LeonardoSpectrum Level 1 version 1999.1j synthesis software to all customers with current subscriptions. Model Technology ModelSim-Altera simulation software will be shipping to customers shortly.

Visit the Altera web site to request a license file to enable any or all of the OEM software tools. A license file will be e-mailed directly to you to enable these synthesis and simulation
capabilities for use with the Altera software. FPGA Express is only available for the PC platform, working with FIXEDPC and FLOATPC products. The LeonardoSpectrum and ModelSim software for Altera are available for PCs and UNIX workstations in fixed or floating configurations.

Synopsys FPGA Express for Altera supports mixed-HDL synthesis for VHDL and Verilog designs. The feature set of the FPGA Express software that Altera ships is identical to the standard FPGA Express software. However, FPGA Express software only targets Altera devices.

For LeonardoSpectrum license files, you can request either VHDL or Verilog support for each Altera subscription, but not can only have support for one HDL per Altera subscription. The LeonardoSpectrum Level 1 for Altera and Level 2 software tools do not support mixed-HDL synthesis. The LeonardoSpectrum Level 1 synthesis tool provided by Altera includes all the features of the LeonardoSpectrum Level 2 configuration, but only allows designers to target Altera devices.

The ModelSim-Altera simulation software consists of the ModelSim PE GUI features including the standard HDL debugging environment and Tcl scripting capability supporting Altera libraries for gate-level simulation. You can request either VHDL or Verilog HDL support within the ModelSim software for each Altera subscription, but not both. The ModelSim-Altera software tools do not support mixed-HDL simulation.

You can indefinitely use versions of the Synopsys FPGA Express software for Altera received during your active subscription. However, you cannot enable versions of FPGA Express released after your subscription expires. This is identical to the licensing for the Quartus and MAX+PLUS II software.

License files for Exemplar Logic LeonardoSpectrum and Model Technology ModelSim software provided by Altera are set to expire 15 months from the date of the license request. These products will no longer operate after expiration. However, you can request a new license and extend the expiration for another 15 months as long as your subscription remains active.

Altera has entered into OEM agreements with Synopsys and Mentor Graphics to provide Altera customers with world-class synthesis and simulation products.

May 2000

News & Views Altera Corporation

DesignTips

Improving Quartus Design Performance

The QuartusTM software version and higher introduces new and improved timingdriven compilation algorithms for core and I/O performance as well as more capability for cliques. In most cases, push-button performance in the Quartus software can achieve desired requirements for core fMAX and I/O timing. Many additional techniques can be used to achieve even better performance in APEXTM designs with the Quartus software, including:
s Timing-driven compilation s Cliques and other logic options s Back-annotation and manual placement

Timing-Driven Compilation

The Quartus software is very flexible, and offers a large number of options that can be set within. You can set a global timing-driven compilation target for the entire design, or several timingdriven compilation target settings, one for each individual clock domain if several exist in the design . Individual clock settings usually provide better fMAX results and are required for multiple clock domain analysis and hold-time validation . For optimal results, experiment with both global and individual settings.
the Speed vs. Area setting, and the Auto-Global Memory Control Signals setting.

Cliques

Version and higher of the Quartus software provides cliques of different target sizes, controlling how tightly you pack the logic. Target areas can be as small as a logic array block LAB or up to half of the device.

You can use cliques with timing-driven compilation on or off. Altera recommends that you enable timing-driven compilation with hierarchical-based cliques based on your knowledge of your design. All cliques except Best cliques, see Figure 1 are considered hard assignments that may create complications if they cannot be met. You may get a no-fit result if too much logic is placed into too small an area i.e., placing 12 logic cells into one LAB . If you are unsure of the size of cliqued logic, use the Best clique type, which allows the Quartus software to modify the size of the clique target as needed.

After the initial compilation results with timingdriven compilation and hierarchical cliques, you

Figure Clique Selection in Assignment Organizer

In the Quartus software version and
higher, you can either select Normal
compilation or Extra effort. The Extra effort
setting usually provides better fMAX results, but may increase compile times up to In either case, you should set the target fMAX about 10% higher than required and vary the target until
you find the best results. If you set the target too
high, though, you may over-constrain the

Quartus software, producing slower results.

Cliques and Other Logic Options

You can use options and settings in the Quartus software to improve results, including cliques,

Altera Corporation News & Views

May 2000
can analyze critical paths, determine logic common between multiple critical paths, and apply a clique to place logic cells closer together see Figure

Figure Cliquing Common Logic Cells

You should add cliques only when your design performance is much slower than what is required avoid assigning logic haphazardly into cliques without verifying that logic cells are not placed into multiple cliques of the same size. This can add more logic into the original clique size, which may result in a no-fit.
Altera is adding to its portfolio of Forward Error Correction functions for wide use in third-generation 3G wireless applications. In addition to the Reed-Solomon and Viterbi cores, the latest addition to this family is the Turbo Encoder ordering code PLSM-TURBO/ENC and Turbo Decoder ordering code PLSMTURBO/DEC megafunctions.

The Turbo MegaCore function is targeted towards 3G wireless applications, satellite communications, digital video broadcast, and sub-marine data transfer applications, where high speed and high data integrity are paramount.

Optimized for the APEXTM family of devices, Altera’s Turbo MegaCore function, like the

Reed-Solomon core, comes with separate encoder and decoder cores, as shown in It is also compliant with the ThirdGeneration Partnership Project 3GPP for error correction on high-speed data services up to megabits per second Mbps .

Because of the dynamic state of the 3GPP, no current 3GPP compliant application-specific standard products ASSPs or ASICs exist. Digital signal processors, hovering around Kbits per second Kbps , cannot achieve the high throughput possible in Altera’s programmable logic devices PLDs .

The Turbo Encoder function is stream-driven and uses a block-based coding scheme. Two interleaved convolutional encoders generate P1

Altera Corporation News & Views

May 2000

Altera News
and P2 parity output streams. These streams can then be punctured to save bandwidth. The 3GPP code rates are approximately 1/3 if puncturing is not used and 1/2 with puncturing.

After depuncturing the received data stream, the information and P1 parity bits are fed into decoder An equalizer not shown in Figure 1 delivers the probabilities of the received values to decoder 1 then has the received bit value and the confidence level of that bit value. Decoder 1 evaluates these results and combines them with the P1 probabilities parity bits , which are fed into decoder 2 with the information bits and the P2 parity bits. After a predefined number of iterations, the decoding process is completed and the output is available.

The purpose of interleaving is to combat burst errors. Convolutional codes are an excellent defense against random errors. However, since errors typically come in bursts, interleavers disperse the corrupt data, making it easier to correct. The turbo decoder interleaver, as defined by 3GPP, is a rigorous algebraic interleaver based on sets of prime numbers. As this function is labor-intensive to implement, it is an essential component of Altera’s Turbo Decoder.

Figure Turbo CODEC Block Diagram

Medium in which noise is introduced.

Interleaver

Encoder 1

Encoder 2

Puncture Turbo Encoder
max-logMAP Decoder 1

De-Puncture

De-Interleaver

Interleaver
max-logMAP Decoder 2 Turbo Decoder

Figure Turbo Decoder Block Diagram

Alpha Memory

Parity Memory

Control Processor
max-logMAP Decoder
3GPP Interleaver

Information Memory

Turbo Decoder Core

Apiori Memory

Altera’s turbo decoder takes advantage of a logarithmic maximal a-posteriori maxlogMAP algorithm see Figure This is a computationally intensive algorithm, which utilizes two banks of memory and Parity memory. Altera’s Turbo MegaCore function gives the user total flexibility with the memory configuration via the Plug-In Manager see Table

Table Turbo Decoder Memory Configuration Examples

Soft Alpha Parity Number Suitable Bits Memory of ESBs Device

On-chip On-chip
70 EP20K300E

Off-chip On-chip
46 EP20K200

Off-chip Off-chip
32 EP20K200
More datasheets: AT25080N-10SC-2.7 | AT25080N-10SI | AT25160N-10SC-2.7 | AT25320-10PC | AT25160-10PC-2.7 | AT25160-10PI | AT25160N-10SC | PF27.0W9 | 2101 | PLMB7000-256


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Datasheet ID: PLMT3000-100NC 517153