EP1M120F484C8A

EP1M120F484C8A Datasheet

EP1M120

Part	Datasheet
EP1M120F484C8A	EP1M120F484C8A (pdf)

Related Parts	Information
EP1M120F484C8ES	EP1M120F484C8ES
EP1M350F780C7ES	EP1M350F780C7ES
EP1M120F484C7ES	EP1M120F484C7ES
EP1M120F484C7A	EP1M120F484C7A
EP1M350F780I6AA	EP1M350F780I6AA

PDF Datasheet Preview
January 2003, ver. Mercury Programmable Logic Device Family Data Sheet • High-performance programmable logic device PLD family see Table 1 Integrated high-speed transceivers with support for clock data recovery CDR at up to gigabits per second Gbps Look-up table LUT -based architecture optimized for high speed Advanced interconnect structure for fast routing of critical paths Enhanced I/O structure for versatile standards and interface support Up to 14,400 logic elements LEs • System-level features Up to four general-purpose phase-locked loops PLLs with programmable multiplication and delay shifting Up to 12 PLL output ports Dedicated multiplier circuitry for high-speed implementation of signed or unsigned multiplication up to 16 x 16 Embedded system blocks ESBs used to implement memory functions including quad-port RAM, true dual-port RAM, firstin first-out FIFO buffers, and content-addressable memory CAM Each ESB contains 4,096 bits and can be split and used as two 2,048-bit unidirectional dual-port RAM blocks Table Mercury Device Features Typical gates HSDI channels LEs ESBs 1 Maximum RAM bits Maximum user I/O pins EP1M120 120,000 8 4,800 12 49,152 303 EP1M350 350,000 18 14,400 28 114,688 486 Note to Table 1 Each ESB can be used for two dual- or single-port RAM blocks. Tools Altera Corporation DS-MERCURY-2.2 Mercury Programmable Logic Device Family Data Sheet ...and More Features • Advanced high-speed I/O features Robust I/O standard support, including LVTTL, PCI up to 66 MHz, 3.3-V AGP in 1x and 2x modes, 3.3-V SSTL-3 and 2.5-V SSTL-2, GTL+, HSTL, CTT, LVDS, LVPECL, and 3.3-V PCML High-speed differential interface HSDI with dedicated circuitry for CDR at up to Gbps for LVDS, LVPECL, and 3.3-V PCML Support for source-synchronous True-LVDSTM circuitry up to 840 megabits per second Mbps for LVDS, LVPECL, and 3.3-V PCML Up to 18 input and 18 output dedicated differential channels of high-speed LVDS, LVPECL, or 3.3-V PCML Built-in termination resistor on HSDI data and clock differential pairs Flexible-LVDSTM circuitry provides 624-Mbps support on up to 100 channels with the EP1M350 device Versatile three-register I/O element IOE supporting double data rate I/O DDRIO , double data-rate DDR SDRAM, zero bus turnaround ZBT SRAM, and quad data rate QDR SRAM • Designed for low-power operation 1.8-V internal supply voltage VCCINT MultiVoltTM I/O interface voltage levels VCCIO compatible with 1.5-V, 1.8-V, 2.5-V, and 3.3-V devices 5.0-V tolerant with external resistor • Advanced interconnect structure Multi-level Interconnect structure providing fast, predictable interconnect delays Optimized high-speed Priority FastTrack Interconnect for routing critical paths in a design Dedicated carry chain that implements arithmetic functions such as fast adders, counters, and comparators automatically used by software tools and megafunctions FastLUTTM connection allowing high speed direct connection between LEs in the same logic array block LAB Leap lines allowing a single LAB to directly drive LEs in adjacent rows The RapidLAB interconnect providing a high-speed connection to a 10-LAB-wide region Dedicated clock and control signal resources, including four dedicated clocks, six dedicated fast global signals, and additional row-global signals Altera Corporation Mercury Programmable Logic Device Family Data Sheet Tables 2 and 3 show the MercuryTM FineLine BGATM device package sizes, options, and I/O pin counts. Table Mercury Package Sizes Feature Pitch mm Area mm2 Length x width mm x mm 484-Pin FineLine BGA 529 23 x 23 780-Pin FineLine BGA 841 29 x 29 Table Mercury Package Options & I/O Count Device EP1M120 EP1M350 484-Pin FineLine BGA 780-Pin FineLine BGA Mercury devices integrate high-speed differential transceivers and support for CDR with a speed-optimized PLD architecture. These transceivers are implemented through the dedicated serializer, deserializer, and clock recovery circuitry in the HSDI and incorporate support for the LVDS, LVPECL, and 3.3-V PCML I/O standards. This circuitry, together with enhanced I/O elements IOEs and support for numerous I/O standards, allows Mercury devices to meet high-speed interface requirements. Mercury devices are the first PLDs optimized for core performance. These LUT-based, enhanced memory devices use a network of fast routing resources to achieve optimal performance. These resources are ideal for data-path, register-intensive, mathematical, digital signal processing DSP , or communications designs.

PDF Datasheet Preview

January 2003, ver.

Mercury

Programmable Logic Device Family

Data Sheet
• High-performance programmable logic device PLD family see Table 1 Integrated high-speed transceivers with support for clock data recovery CDR at up to gigabits per second Gbps Look-up table LUT -based architecture optimized for high speed Advanced interconnect structure for fast routing of critical paths Enhanced I/O structure for versatile standards and interface support Up to 14,400 logic elements LEs
• System-level features Up to four general-purpose phase-locked loops PLLs with programmable multiplication and delay shifting Up to 12 PLL output ports Dedicated multiplier circuitry for high-speed implementation of signed or unsigned multiplication up to 16 x 16 Embedded system blocks ESBs used to implement memory functions including quad-port RAM, true dual-port RAM, firstin first-out FIFO buffers, and content-addressable memory CAM Each ESB contains 4,096 bits and can be split and used as two 2,048-bit unidirectional dual-port RAM blocks

Table Mercury Device Features

Typical gates HSDI channels LEs ESBs 1 Maximum RAM bits Maximum user I/O pins

EP1M120
120,000 8
4,800 12
49,152 303

EP1M350
350,000 18
14,400 28
114,688 486

Note to Table 1 Each ESB can be used for two dual- or single-port RAM blocks.

Tools

Altera Corporation

DS-MERCURY-2.2

Mercury Programmable Logic Device Family Data Sheet
...and More Features
• Advanced high-speed I/O features Robust I/O standard support, including LVTTL, PCI up to 66 MHz, 3.3-V AGP in 1x and 2x modes, 3.3-V SSTL-3 and 2.5-V SSTL-2, GTL+, HSTL, CTT, LVDS, LVPECL, and 3.3-V PCML High-speed differential interface HSDI with dedicated circuitry for CDR at up to Gbps for LVDS, LVPECL, and 3.3-V PCML Support for source-synchronous True-LVDSTM circuitry up to 840 megabits per second Mbps for LVDS, LVPECL, and 3.3-V PCML Up to 18 input and 18 output dedicated differential channels of high-speed LVDS, LVPECL, or 3.3-V PCML Built-in termination resistor on HSDI data and clock differential pairs Flexible-LVDSTM circuitry provides 624-Mbps support on up to 100 channels with the EP1M350 device Versatile three-register I/O element IOE supporting double data rate I/O DDRIO , double data-rate DDR SDRAM, zero bus turnaround ZBT SRAM, and quad data rate QDR SRAM
• Designed for low-power operation 1.8-V internal supply voltage VCCINT MultiVoltTM I/O interface voltage levels VCCIO compatible with 1.5-V, 1.8-V, 2.5-V, and 3.3-V devices 5.0-V tolerant with external resistor
• Advanced interconnect structure Multi-level Interconnect structure providing fast, predictable interconnect delays Optimized high-speed Priority FastTrack Interconnect for routing critical paths in a design Dedicated carry chain that implements arithmetic functions such as fast adders, counters, and comparators automatically used by software tools and megafunctions FastLUTTM connection allowing high speed direct connection between LEs in the same logic array block LAB Leap lines allowing a single LAB to directly drive LEs in adjacent rows The RapidLAB interconnect providing a high-speed connection to a 10-LAB-wide region Dedicated clock and control signal resources, including four dedicated clocks, six dedicated fast global signals, and additional row-global signals

Altera Corporation

Mercury Programmable Logic Device Family Data Sheet

Tables 2 and 3 show the MercuryTM FineLine BGATM device package sizes, options, and I/O pin counts.

Table Mercury Package Sizes Feature

Pitch mm Area mm2 Length x width mm x mm
484-Pin FineLine BGA
529 23 x 23
780-Pin FineLine BGA
841 29 x 29

Table Mercury Package Options & I/O Count

Device

EP1M120 EP1M350
484-Pin FineLine BGA
780-Pin FineLine BGA

Mercury devices integrate high-speed differential transceivers and support for CDR with a speed-optimized PLD architecture. These transceivers are implemented through the dedicated serializer, deserializer, and clock recovery circuitry in the HSDI and incorporate support for the LVDS, LVPECL, and 3.3-V PCML I/O standards. This circuitry, together with enhanced I/O elements IOEs and support for numerous I/O standards, allows Mercury devices to meet high-speed interface requirements.

Mercury devices are the first PLDs optimized for core performance. These LUT-based, enhanced memory devices use a network of fast routing resources to achieve optimal performance. These resources are ideal for data-path, register-intensive, mathematical, digital signal processing DSP , or communications designs.

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Datasheet ID: EP1M120F484C8A 517152