EPM7256ERC208-12PY

EPM7256ERC208-12PY Datasheet

Feature EPM7032

Part	Datasheet
EPM7256ERC208-12PY	EPM7256ERC208-12PY (pdf)

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PDF Datasheet Preview
September 2005, ver. MAX 7000 Programmable Logic Device Family Data Sheet Features... f • High-performance, EEPROM-based programmable logic devices PLDs based on second-generation architecture • 5.0-V in-system programmability ISP through the built-in IEEE Std. Joint Test Action Group JTAG interface available in MAX 7000S devices ISP circuitry compatible with IEEE Std. 1532 • Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices • Built-in JTAG boundary-scan test BST circuitry in MAX 7000S devices with 128 or more macrocells • Complete EPLD family with logic densities ranging from 600 to 5,000 usable gates see Tables 1 and 2 • 5-ns pin-to-pin logic delays with up to 175.4-MHz counter frequencies including interconnect • PCI-compliant devices available For information on in-system programmable 3.3-V MAX 7000A or 2.5-V MAX 7000B devices, see the MAX 7000A Programmable Logic Device Family Data Sheet or the MAX 7000B Programmable Logic Device Family Data Sheet. Table MAX 7000 Device Features Feature EPM7032 Usable gates Macrocells Logic array blocks Maximum user I/O pins tPD ns tSU ns tFSU ns tCO1 ns fCNT MHz EPM7064 1,250 EPM7096 EPM7128E EPM7160E EPM7192E EPM7256E 1,800 2,500 3,200 3,750 5,000 Altera Corporation DS-MAX7000-6.7 MAX 7000 Programmable Logic Device Family Data Sheet Table MAX 7000S Device Features Usable gates Macrocells Logic array blocks Maximum user I/O pins tPD ns tSU ns tFSU ns tCO1 ns fCNT MHz EPM7032S 600 32 2 EPM7064S 1,250 64 4 EPM7128S 2,500 128 EPM7160S 3,200 160 10 EPM7192S In-system programming can be accomplished with either an adaptive or constant algorithm. An adaptive algorithm reads information from the unit and adapts subsequent programming steps to achieve the fastest possible programming time for that unit. Because some in-circuit testers cannot support an adaptive algorithm, Altera offers devices tested with a constant algorithm. Devices tested to the constant algorithm have an “F” suffix in the ordering code. The JamTM Standard Test and Programming Language STAPL can be used to program MAX 7000S devices with in-circuit testers, PCs, or embedded processor. Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet For more information on using the Jam language, refer to AN 122 Using Jam STAPL for ISP & ICR via an Embedded Processor. The ISP circuitry in MAX 7000S devices is compatible with IEEE Std. 1532 specification. The IEEE Std. 1532 is a standard developed to allow concurrent ISP between multiple PLD vendors. Programming Sequence During in-system programming, instructions, addresses, and data are shifted into the MAX 7000S device through the TDI input pin. Data is shifted out through the TDO output pin and compared against the expected data. Programming a pattern into the device requires the following six ISP stages. A stand-alone verification of a programmed pattern involves only stages 1, 2, 5, and Enter ISP. The enter ISP stage ensures that the I/O pins transition smoothly from user mode to ISP mode. The enter ISP stage requires 1 ms. Check ID. Before any program or verify process, the silicon ID is checked. The time required to read this silicon ID is relatively small compared to the overall programming time. Bulk Erase. Erasing the device in-system involves shifting in the instructions to erase the device and applying one erase pulse of 100 ms. Program. Programming the device in-system involves shifting in the address and data and then applying the programming pulse to program the EEPROM cells. This process is repeated for each EEPROM address. Verify. Verifying an Altera device in-system involves shifting in addresses, applying the read pulse to verify the EEPROM cells, and shifting out the data for comparison. This process is repeated for each EEPROM address. Exit ISP. An exit ISP stage ensures that the I/O pins transition smoothly from ISP mode to user mode. The exit ISP stage requires 1 ms. Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Programming Times The time required to implement each of the six programming stages can be broken into the following two elements: • A pulse time to erase, program, or read the EEPROM cells. • A shifting time based on the test clock TCK frequency and the number of TCK cycles to shift instructions, address, and data into the device. By combining the pulse and shift times for each of the programming stages, the program or verify time can be derived as a function of the TCK frequency, the number of devices, and specific target device s . Because different ISP-capable devices have a different number of EEPROM cells, both the total fixed and total variable times are unique for a single device. Programming a Single MAX 7000S Device The time required to program a single MAX 7000S device in-system can be calculated from the following formula: tPROG tPPULSE where tPROG tPPULSE CyclePTCK fTCK = Programming time = Sum of the fixed times to erase, program, and verify the EEPROM cells = Number of TCK cycles to program a device = TCK frequency The ISP times for a stand-alone verification of a single MAX 7000S device can be calculated from the following formula: tVER tVPULSE where tVER = Verify time tVPULSE = Sum of the fixed times to verify the EEPROM cells CycleVTCK = Number of TCK cycles to verify a device Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet The programming times described in Tables 6 through 8 are associated with the worst-case method using the enhanced ISP algorithm. Table MAX 7000S tPULSE & CycleTCK Values

PDF Datasheet Preview

September 2005, ver.

MAX 7000

Programmable Logic Device Family

Data Sheet

Features... f
• High-performance, EEPROM-based programmable logic devices PLDs based on second-generation architecture
• 5.0-V in-system programmability ISP through the built-in IEEE Std. Joint Test Action Group JTAG interface available in MAX 7000S devices ISP circuitry compatible with IEEE Std. 1532
• Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices
• Built-in JTAG boundary-scan test BST circuitry in MAX 7000S devices with 128 or more macrocells
• Complete EPLD family with logic densities ranging from 600 to 5,000 usable gates see Tables 1 and 2
• 5-ns pin-to-pin logic delays with up to 175.4-MHz counter frequencies including interconnect
• PCI-compliant devices available

For information on in-system programmable 3.3-V MAX 7000A or 2.5-V MAX 7000B devices, see the MAX 7000A Programmable Logic Device Family Data Sheet or the MAX 7000B Programmable Logic Device Family Data Sheet.

Table MAX 7000 Device Features

Feature EPM7032

Usable gates

Macrocells Logic array blocks

Maximum user I/O pins
tPD ns tSU ns tFSU ns tCO1 ns fCNT MHz

EPM7064
1,250

EPM7096 EPM7128E EPM7160E EPM7192E EPM7256E
1,800
2,500
3,200
3,750
5,000

Altera Corporation

DS-MAX7000-6.7

MAX 7000 Programmable Logic Device Family Data Sheet

Table MAX 7000S Device Features

Usable gates Macrocells Logic array blocks Maximum user I/O pins tPD ns tSU ns tFSU ns tCO1 ns fCNT MHz

EPM7032S
600 32 2

EPM7064S
1,250 64 4

EPM7128S
2,500 128

EPM7160S
3,200 160 10

EPM7192S
In-system programming can be accomplished with either an adaptive or constant algorithm. An adaptive algorithm reads information from the unit and adapts subsequent programming steps to achieve the fastest possible programming time for that unit. Because some in-circuit testers cannot support an adaptive algorithm, Altera offers devices tested with a constant algorithm. Devices tested to the constant algorithm have an “F” suffix in the ordering code.

The JamTM Standard Test and Programming Language STAPL can be used to program MAX 7000S devices with in-circuit testers, PCs, or embedded processor.

Altera Corporation

MAX 7000 Programmable Logic Device Family Data Sheet

For more information on using the Jam language, refer to AN 122 Using Jam STAPL for ISP & ICR via an Embedded Processor.

The ISP circuitry in MAX 7000S devices is compatible with IEEE Std. 1532 specification. The IEEE Std. 1532 is a standard developed to allow concurrent ISP between multiple PLD vendors.

Programming Sequence

During in-system programming, instructions, addresses, and data are shifted into the MAX 7000S device through the TDI input pin. Data is shifted out through the TDO output pin and compared against the expected data.

Programming a pattern into the device requires the following six ISP stages. A stand-alone verification of a programmed pattern involves only stages 1, 2, 5, and

Enter ISP. The enter ISP stage ensures that the I/O pins transition smoothly from user mode to ISP mode. The enter ISP stage requires 1 ms.

Check ID. Before any program or verify process, the silicon ID is checked. The time required to read this silicon ID is relatively small compared to the overall programming time.

Bulk Erase. Erasing the device in-system involves shifting in the instructions to erase the device and applying one erase pulse of 100 ms.

Program. Programming the device in-system involves shifting in the address and data and then applying the programming pulse to program the EEPROM cells. This process is repeated for each EEPROM address.

Verify. Verifying an Altera device in-system involves shifting in addresses, applying the read pulse to verify the EEPROM cells, and shifting out the data for comparison. This process is repeated for each EEPROM address.

Exit ISP. An exit ISP stage ensures that the I/O pins transition smoothly from ISP mode to user mode. The exit ISP stage requires 1 ms.

Altera Corporation

MAX 7000 Programmable Logic Device Family Data Sheet

Programming Times

The time required to implement each of the six programming stages can be broken into the following two elements:
• A pulse time to erase, program, or read the EEPROM cells.
• A shifting time based on the test clock TCK frequency and the
number of TCK cycles to shift instructions, address, and data into the device.

By combining the pulse and shift times for each of the programming stages, the program or verify time can be derived as a function of the TCK frequency, the number of devices, and specific target device s . Because different ISP-capable devices have a different number of EEPROM cells, both the total fixed and total variable times are unique for a single device.

Programming a Single MAX 7000S Device

The time required to program a single MAX 7000S device in-system can be calculated from the following formula:
tPROG
tPPULSE
where tPROG tPPULSE

CyclePTCK fTCK
= Programming time = Sum of the fixed times to erase, program, and
verify the EEPROM cells = Number of TCK cycles to program a device = TCK frequency

The ISP times for a stand-alone verification of a single MAX 7000S device can be calculated from the following formula:
tVER
tVPULSE
where tVER
= Verify time
tVPULSE = Sum of the fixed times to verify the EEPROM cells

CycleVTCK = Number of TCK cycles to verify a device

Altera Corporation

MAX 7000 Programmable Logic Device Family Data Sheet

The programming times described in Tables 6 through 8 are associated with the worst-case method using the enhanced ISP algorithm.

Table MAX 7000S tPULSE & CycleTCK Values

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Datasheet ID: EPM7256ERC208-12PY 517148