EPF6010AFC256-3

EPF6010AFC256-3 Datasheet


EPF6010A

Part Datasheet
EPF6010AFC256-3 EPF6010AFC256-3 EPF6010AFC256-3 (pdf)
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PDF Datasheet Preview
March 2001, ver.

FLEX 6000

Programmable Logic Device Family

Data Sheet

Features...
• Provides an ideal low-cost, programmable alternative to highvolume gate array applications and allows fast design changes during prototyping or design testing
• Product features Register-rich, look-up table- LUT- based architecture that increases device area efficiency Typical gates ranging from 5,000 to 24,000 gates see Table 1 Built-in low-skew clock distribution tree 100% functional testing of all devices test vectors or scan chains are not required

Table FLEX 6000 Device Features

EPF6010A

EPF6016

EPF6016A

EPF6024A

Typical gates 1
10,000
16,000
16,000
24,000

Logic elements LEs
1,320
1,320
1,960

Maximum I/O pins

Supply voltage VCCINT

Note 1 The embedded IEEE Std. JTAG circuitry adds up to 14,000 gates in addition to the listed typical gates.

Altera Corporation

A-DS-F6000-04.1

FLEX 6000 Programmable Logic Device Family Data Sheet
...and More Features
• Powerful I/O pins Individual tri-state output enable control for each pin Programmable output slew-rate control to reduce switching noise Fast path from register to I/O pin for fast clock-to-output time
• Flexible interconnect continuous routing structure for fast, predictable interconnect delays Dedicated carry chain that implements arithmetic functions such as fast adders, counters, and comparators automatically used by software tools and megafunctions Dedicated cascade chain that implements high-speed, high-fanin logic functions automatically used by software tools and megafunctions Tri-state emulation that implements internal tri-state networks Four low-skew global paths for clock, clear, preset, or logic signals
• Software design support and automatic place-and-route provided by Altera’s development system for Windows-based PCs, Sun SPARCstations, and HP 9000 Series 700/800
• Flexible package options Available in a variety of packages with 100 to 256 pins, including the innovative FineLine BGATM packages see Table 2 SameFrameTM pin-compatibility with other 6000 devices across device densities and pin counts Thin quad flat pack TQFP , plastic quad flat pack PQFP , and ball-grid array BGA packages see Table 2 Footprint- and pin-compatibility with other FLEX 6000 devices in the same package
• Additional design entry and simulation support provided by EDIF 2 0 and 3 0 netlist files, the library of parameterized modules LPM , Verilog HDL, VHDL, DesignWare components, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, VeriBest, and Viewlogic

Table FLEX 6000 Package Options & I/O Pin Count

Device

EPF6010A EPF6016 EPF6016A EPF6024A
100-Pin TQFP
100-Pin FineLine BGA
144-Pin TQFP
102 117
208-Pin PQFP
More datasheets: IPC-6806BP-25ZCE | IPC-6806SB-15ZBE | 37717 | 245110-08-03.00 | A1642LKNTN-I2-T | A1642LKNTN-I1-T | 17-215SYGC/S530-E2/TR8 | EPF6010AFC100-1 | EPF6010AFC100-2 | EPF6010AFC256-1


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Datasheet ID: EPF6010AFC256-3 517144