EPF10K30EFI256-3

EPF10K30EFI256-3 Datasheet

EPF10K30E

Part	Datasheet
EPF10K30EFI256-3	EPF10K30EFI256-3 (pdf)

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January 2003, ver. FLEX 10KE Embedded Programmable Logic Device Data Sheet Features... f • Embedded programmable logic devices PLDs , providing system-on-a-programmable-chip SOPC integration in a single device Enhanced embedded array for implementing megafunctions such as efficient memory and specialized logic functions Dual-port capability with up to 16-bit width per embedded array block EAB Logic array for general logic functions • High density 30,000 to 200,000 typical gates see Tables 1 and 2 Up to 98,304 RAM bits 4,096 bits per EAB , all of which can be used without reducing logic capacity For information on 5.0-V 10K or 3.3-V FLEX 10KA devices, see the FLEX 10K Embedded Programmable Logic Family Data Sheet. Table FLEX 10KE Device Features Typical gates 1 Maximum system gates Logic elements LEs EABs Total RAM bits Maximum user I/O pins Altera Corporation DS-F10KE-2.5 EPF10K30E 30,000 119,000 1,728 6 24,576 220 EPF10K50E EPF10K50S 50,000 199,000 2,880 10 40,960 254 FLEX 10KE Embedded Programmable Logic Devices Data Sheet Table FLEX 10KE Device Features Typical gates 1 Maximum system gates Logic elements LEs EABs Total RAM bits Maximum user I/O pins EPF10K100E 2 100,000 257,000 4,992 12 49,152 338 EPF10K130E 130,000 342,000 6,656 16 65,536 413 EPF10K200E EPF10K200S 200,000 513,000 9,984 24 98,304 470 Note to tables 1 The embedded IEEE Std. JTAG circuitry adds up to 31,250 gates in addition to the listed typical or maximum system gates. 2 New EPF10K100B designs should use EPF10K100E devices. ...and More Features Fabricated on an advanced process and operate with a 2.5-V internal supply voltage In-circuit reconfigurability ICR via external configuration devices, intelligent controller, or JTAG port ClockLockTM and ClockBoostTM options for reduced clock delay/skew and clock multiplication All FLEX 10KE devices, except EPF10K50E and EPF10K200E devices, support ClockLock and ClockBoost circuitry. EPF10K50S and EPF10K200S devices support this circuitry. Devices that support ClockLock and ClockBoost circuitry are distinguished with an “X” suffix in the ordering code for instance, the EPF10K200SFC672-1X device supports this circuit. The ClockLock and ClockBoost features in FLEX 10KE devices are enabled through the Altera software. External devices are not required to use these features. The output of the ClockLock and ClockBoost circuits is not available at any of the device pins. The ClockLock and ClockBoost circuitry locks onto the rising edge of the incoming clock. The circuit output can drive the clock inputs of registers only the generated clock cannot be gated or inverted. The dedicated clock pin GCLK1 supplies the clock to the ClockLock and ClockBoost circuitry. When the dedicated clock pin is driving the ClockLock or ClockBoost circuitry, it cannot drive elsewhere in the device. For designs that require both a multiplied and non-multiplied clock, the clock trace on the board can be connected to the GCLK1 pin. In the Altera software, the GCLK1 pin can feed both the ClockLock and ClockBoost circuitry in the FLEX 10KE device. However, when both circuits are used, the other clock pin cannot be used. Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet ClockLock & ClockBoost Timing Parameters For the ClockLock and ClockBoost circuitry to function properly, the incoming clock must meet certain requirements. If these specifications are not met, the circuitry may not lock onto the incoming clock, which generates an erroneous clock within the device. The clock generated by the ClockLock and ClockBoost circuitry must also meet certain specifications. If the incoming clock meets these requirements during configuration, the ClockLock and ClockBoost circuitry will lock onto the clock during configuration. The circuit will be ready for use immediately after configuration. Figure 19 shows the incoming and generated clock specifications. Figure Specifications for Incoming & Generated Clocks The tI parameter refers to the nominal input clock period the tO parameter refers to the nominal output clock period. tCLK1 tINDUTY tI ± fCLKDEV Input Clock tR tF tOUTDUTY tI ± tINCLKSTB ClockLockGenerated Clock tO + tJITTER tO tJITTER Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet Tables 12 and 13 summarize the ClockLock and ClockBoost parameters for -1 and -2 speed-grade devices, respectively. Table ClockLock & ClockBoost Parameters for -1 Speed-Grade Devices Parameter tR tF t INDUTY f CLK1 fCLK2 f CLKDEV t INCLKSTB t LOCK t JITTER Input rise time Input fall time Input duty cycle Input clock frequency ClockBoost clock multiplication factor equals 1 Input clock frequency ClockBoost clock multiplication factor equals 2 Input deviation from user specification in the MAX+PLUS II software 1 Input clock stability measured between adjacent clocks Time required for ClockLock or ClockBoost to acquire lock 3 Jitter on ClockLock or ClockBoost- generated clock 4 Condition tINCLKSTB < 100 tINCLKSTB < 50 40 25 tOUTDUTY Duty cycle for ClockLock or ClockBoost-generated clock Unit 25,000 2 PPM 200 4 Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet

PDF Datasheet Preview

January 2003, ver.

FLEX 10KE

Embedded Programmable Logic Device

Data Sheet

Features... f
• Embedded programmable logic devices PLDs , providing system-on-a-programmable-chip SOPC integration in a single device Enhanced embedded array for implementing megafunctions such as efficient memory and specialized logic functions Dual-port capability with up to 16-bit width per embedded array block EAB Logic array for general logic functions
• High density 30,000 to 200,000 typical gates see Tables 1 and 2 Up to 98,304 RAM bits 4,096 bits per EAB , all of which can be used without reducing logic capacity

For information on 5.0-V 10K or 3.3-V FLEX 10KA devices, see the FLEX 10K Embedded Programmable Logic Family Data Sheet.

Table FLEX 10KE Device Features

Typical gates 1 Maximum system gates Logic elements LEs EABs Total RAM bits Maximum user I/O pins

Altera Corporation

DS-F10KE-2.5

EPF10K30E
30,000 119,000
1,728 6
24,576 220

EPF10K50E EPF10K50S
50,000 199,000
2,880 10
40,960 254

FLEX 10KE Embedded Programmable Logic Devices Data Sheet

Table FLEX 10KE Device Features

Typical gates 1 Maximum system gates Logic elements LEs EABs Total RAM bits Maximum user I/O pins

EPF10K100E 2
100,000 257,000
4,992 12
49,152 338

EPF10K130E
130,000 342,000
6,656 16
65,536 413

EPF10K200E EPF10K200S
200,000 513,000
9,984 24
98,304 470

Note to tables 1 The embedded IEEE Std. JTAG circuitry adds up to 31,250 gates in addition to the listed typical or maximum
system gates. 2 New EPF10K100B designs should use EPF10K100E devices.
...and More Features

Fabricated on an advanced process and operate with a 2.5-V internal supply voltage

In-circuit reconfigurability ICR via external configuration devices, intelligent controller, or JTAG port

ClockLockTM and ClockBoostTM options for reduced clock delay/skew and clock multiplication
All FLEX 10KE devices, except EPF10K50E and EPF10K200E devices, support ClockLock and ClockBoost circuitry. EPF10K50S and EPF10K200S devices support this circuitry. Devices that support ClockLock and ClockBoost circuitry are distinguished with an “X” suffix in the ordering code for instance, the EPF10K200SFC672-1X device supports this circuit.

The ClockLock and ClockBoost features in FLEX 10KE devices are enabled through the Altera software. External devices are not required to use these features. The output of the ClockLock and ClockBoost circuits is not available at any of the device pins.

The ClockLock and ClockBoost circuitry locks onto the rising edge of the incoming clock. The circuit output can drive the clock inputs of registers only the generated clock cannot be gated or inverted.

The dedicated clock pin GCLK1 supplies the clock to the ClockLock and ClockBoost circuitry. When the dedicated clock pin is driving the ClockLock or ClockBoost circuitry, it cannot drive elsewhere in the device.

For designs that require both a multiplied and non-multiplied clock, the clock trace on the board can be connected to the GCLK1 pin. In the Altera software, the GCLK1 pin can feed both the ClockLock and ClockBoost circuitry in the FLEX 10KE device. However, when both circuits are used, the other clock pin cannot be used.

Altera Corporation

FLEX 10KE Embedded Programmable Logic Devices Data Sheet

ClockLock & ClockBoost Timing Parameters

For the ClockLock and ClockBoost circuitry to function properly, the incoming clock must meet certain requirements. If these specifications are not met, the circuitry may not lock onto the incoming clock, which generates an erroneous clock within the device. The clock generated by the ClockLock and ClockBoost circuitry must also meet certain specifications. If the incoming clock meets these requirements during configuration, the ClockLock and ClockBoost circuitry will lock onto the clock during configuration. The circuit will be ready for use immediately after configuration. Figure 19 shows the incoming and generated clock specifications.

Figure Specifications for Incoming & Generated Clocks

The tI parameter refers to the nominal input clock period the tO parameter refers to the nominal output clock period.
tCLK1
tINDUTY
tI ± fCLKDEV

Input Clock
tR tF tOUTDUTY
tI ± tINCLKSTB

ClockLockGenerated Clock
tO + tJITTER tO tJITTER

Altera Corporation

FLEX 10KE Embedded Programmable Logic Devices Data Sheet

Tables 12 and 13 summarize the ClockLock and ClockBoost parameters for -1 and -2 speed-grade devices, respectively.

Table ClockLock & ClockBoost Parameters for -1 Speed-Grade Devices

Parameter
tR tF t INDUTY f CLK1 fCLK2 f CLKDEV
t INCLKSTB t LOCK t JITTER

Input rise time Input fall time Input duty cycle Input clock frequency ClockBoost clock multiplication factor equals 1 Input clock frequency ClockBoost clock multiplication factor equals 2 Input deviation from user specification in the MAX+PLUS II
software 1

Input clock stability measured between adjacent clocks Time required for ClockLock or

ClockBoost to acquire lock 3

Jitter on ClockLock or ClockBoost-
generated clock 4

Condition
tINCLKSTB < 100 tINCLKSTB < 50
40 25
tOUTDUTY Duty cycle for ClockLock or ClockBoost-generated clock

Unit
25,000 2 PPM
200 4

Altera Corporation

FLEX 10KE Embedded Programmable Logic Devices Data Sheet

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Datasheet ID: EPF10K30EFI256-3 517143