EPF8636ALC84-2

EPF8636ALC84-2 Datasheet

EPF8282A EPF8452A EPF8282AV

Part	Datasheet
EPF8636ALC84-2	EPF8636ALC84-2 (pdf)

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PDF Datasheet Preview
January 2003, ver. FLEX 8000 Programmable Logic Device Family Data Sheet Features... • Low-cost, high-density, register-rich CMOS programmable logic device PLD family see Table 1 2,500 to 16,000 usable gates 282 to 1,500 registers • System-level features In-circuit reconfigurability ICR via external configuration devices or intelligent controller Fully compliant with the peripheral component interconnect Special Interest Group PCI SIG PCI Local Bus Specification, Built-in Joint Test Action Group JTAG boundary-scan test BST circuitry compliant with IEEE Std. on selected devices MultiVoltTM I/O interface enabling device core to run at V, while I/O pins are compatible with 5.0-V and 3.3-V logic levels Low power consumption typical specification is mA or less in FLEX 8000 standby mode • Flexible interconnect Interconnect continuous routing structure for fast, predictable interconnect delays Dedicated carry chain that implements arithmetic functions such as fast adders, counters, and comparators automatically used by software tools and megafunctions Dedicated cascade chain that implements high-speed, high-fan-in logic functions automatically used by software tools and megafunctions Tri-state emulation that implements internal tri-state nets • Powerful I/O pins • Programmable output slew-rate control reduces switching noise Table FLEX 8000 Device Features EPF8282A EPF8452A EPF8282AV Usable gates 2,500 4,000 Flipflops Logic array blocks LABs Logic elements LEs

PDF Datasheet Preview

January 2003, ver.

FLEX 8000

Programmable Logic Device Family

Data Sheet

Features...
• Low-cost, high-density, register-rich CMOS programmable logic
device PLD family see Table 1
2,500 to 16,000 usable gates
282 to 1,500 registers
• System-level features

In-circuit reconfigurability ICR via external configuration
devices or intelligent controller

Fully compliant with the peripheral component interconnect

Special Interest Group PCI SIG PCI Local Bus Specification,

Built-in Joint Test Action Group JTAG boundary-scan test BST
circuitry compliant with IEEE Std. on selected devices

MultiVoltTM I/O interface enabling device core to run at V,
while I/O pins are compatible with 5.0-V and 3.3-V logic levels

Low power consumption typical specification is mA or less in

FLEX 8000
standby mode
• Flexible interconnect

Interconnect continuous routing structure for fast,
predictable interconnect delays

Dedicated carry chain that implements arithmetic functions such
as fast adders, counters, and comparators automatically used by
software tools and megafunctions

Dedicated cascade chain that implements high-speed, high-fan-in
logic functions automatically used by software tools and
megafunctions

Tri-state emulation that implements internal tri-state nets
• Powerful I/O pins
• Programmable output slew-rate control reduces switching noise

Table FLEX 8000 Device Features

EPF8282A EPF8452A EPF8282AV

Usable gates
2,500
4,000

Flipflops

Logic array blocks LABs

Logic elements LEs

More datasheets: 0603-4N7J | 0603-5N1J | 0603-5N6J | 0603-6N8J | 0603-121J | 0603-1N8J | 0603-101J | EPF8452ATC100-2 | EPF8820AQC208-4AA | EPF8820ABC225-2

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Datasheet ID: EPF8636ALC84-2 517141