EPXA1F484C2

EPXA1F484C2 Datasheet

EPXA1

Part	Datasheet
EPXA1F484C2	EPXA1F484C2 (pdf)

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EPXA4F672C2	EPXA4F672C2
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EPXA4F1020C2ES	EPXA4F1020C2ES
EPXA1F484C3	EPXA1F484C3

PDF Datasheet Preview
Excalibur Device Overview May 2002, ver. Data Sheet Features... Altera Corporation DS-EXCARM-2.0 I Combination of a world-class RISC processor system with industryleading programmable logic on a single device I Industry-standard ARM922T 32-bit RISC processor core operating at up to 200 MHz ARMv4T instruction set with extensions Memory management unit MMU included for real-time operating system RTOS support Harvard cache architecture with 64-way set associative separate 8-Kbyte instruction and 8-Kbyte data caches I APEX 20KE-like programmable logic architecture ranging from 100,000 to 1,000,000 gates see Table 1 on page 3 I Advanced bus architecture based on advanced microcontroller bus architecture AMBA high-performance bus AHB I Embedded programmable on-chip peripherals ETM9 embedded trace module to assist software debugging Flexible interrupt controller Universal asynchronous receiver/transmitter UART General-purpose timer Watchdog timer I Advanced memory support Internal single-port SRAM up to 256 Kbytes Internal dual-port SRAM up to 128 Kbytes Internal SDRAM controller - Single data-rate SDR and double data-rate DDR support - Up to 512 Mbytes - Data rates to 133 266 MHz Expansion bus interface EBI - Compatible with industry-standard flash memory, SRAMs, and peripheral devices - Four devices, each up to 32 Mbytes I PLD configuration/reconfiguration possible via the embedded processor software I Fully configurable memory map I Extensive embedded system debug facilities SignalTap embedded logic analyzer JTAG processor debug support Real-time data/instruction processor trace Background debug monitoring via the IEEE Std. JTAG interface Excalibur Device Overview I Multiple and separate clock domains controlled by softwareprogrammable phased-lock loops PLLs for embedded processor, SDRAM, and PLD ClockBoost circuitry provides clock multiplication for the embedded stripe and the PLD ClockLock circuitry reduces clock delay and skew in the PLD I Advanced packaging options see Tables 2 and 3 on page 3 I 1.8-V supply voltage, but many I/O standards supported: SSTL-3 LVTTL GTL+ LVDS I SOPC Builder system development tool Intuitive graphical user interface GUI simplifies system definition and customization Wizard interface facilitates function customization for each component Automatically-generated logic integrates processors, memories, peripherals, IP cores, on-chip buses and bus arbiters VHDL or Verilog HDL code created for system connection Software develoment environment generated to match the target hardware I Extended Quartus II development environment for Excalibur support Integrated hardware and software development environment Plug-In interface configures the embedded processor, PLD, bus connections, and peripherals C/C++ compiler, source-level debugger, and RTOS support This document provides updated information about Excalibur devices and should be used together with the APEX 20K Programmable Logic Device Family Data Sheet. Altera Corporation Excalibur Device Overview Table Excalibur Device Overview Processor Maximum operating frequency Single-port SRAM Dual-port SRAM Typical gates Logic elements LEs Embedded system blocks ESBs Maximum system gates Maximum user I/Os 1 UART, timer, watchdog timer JTAG debug module Embedded trace module General purpose I/O Port Low-power PLL EPXA1 ARM922T 200 MHz 32 Kbytes 16 Kbytes 100,000 4,160 26 263,000 246 Yes 4 bits Yes Note 1 Maximum available user I/Os = shared stripe I/O + PLD I/O EPXA4 ARM922T 200 MHz 128 Kbytes 64 Kbytes 400,000 16,640 104 1,052,000 488 Yes 8 bits EPXA10 ARM922T 200 MHz 256 Kbytes 128 Kbytes 1,000,000 38,400

PDF Datasheet Preview

Excalibur Device Overview

May 2002, ver.

Data Sheet

Features...

Altera Corporation

DS-EXCARM-2.0

I Combination of a world-class RISC processor system with industryleading programmable logic on a single device

I Industry-standard ARM922T 32-bit RISC processor core operating at up to 200 MHz ARMv4T instruction set with extensions Memory management unit MMU included for real-time operating system RTOS support Harvard cache architecture with 64-way set associative separate 8-Kbyte instruction and 8-Kbyte data caches

I APEX 20KE-like programmable logic architecture ranging from 100,000 to 1,000,000 gates see Table 1 on page 3

I Advanced bus architecture based on advanced microcontroller bus architecture AMBA high-performance bus AHB

I Embedded programmable on-chip peripherals ETM9 embedded trace module to assist software debugging Flexible interrupt controller Universal asynchronous receiver/transmitter UART General-purpose timer Watchdog timer

I Advanced memory support Internal single-port SRAM up to 256 Kbytes Internal dual-port SRAM up to 128 Kbytes Internal SDRAM controller - Single data-rate SDR and double data-rate DDR support - Up to 512 Mbytes - Data rates to 133 266 MHz Expansion bus interface EBI - Compatible with industry-standard flash memory, SRAMs, and peripheral devices - Four devices, each up to 32 Mbytes

I PLD configuration/reconfiguration possible via the embedded processor software

I Fully configurable memory map I Extensive embedded system debug facilities

SignalTap embedded logic analyzer JTAG processor debug support Real-time data/instruction processor trace Background debug monitoring via the IEEE Std. JTAG
interface

Excalibur Device Overview

I Multiple and separate clock domains controlled by softwareprogrammable phased-lock loops PLLs for embedded processor, SDRAM, and PLD ClockBoost circuitry provides clock multiplication for the embedded stripe and the PLD ClockLock circuitry reduces clock delay and skew in the PLD

I Advanced packaging options see Tables 2 and 3 on page 3 I 1.8-V supply voltage, but many I/O standards supported:

SSTL-3 LVTTL GTL+ LVDS I SOPC Builder system development tool Intuitive graphical user interface GUI simplifies system
definition and customization Wizard interface facilitates function customization for each
component Automatically-generated logic integrates processors,
memories, peripherals, IP cores, on-chip buses and bus arbiters VHDL or Verilog HDL code created for system connection Software develoment environment generated to match the target hardware I Extended Quartus II development environment for Excalibur support Integrated hardware and software development environment Plug-In interface configures the embedded processor, PLD, bus connections, and peripherals C/C++ compiler, source-level debugger, and RTOS support

This document provides updated information about Excalibur devices and should be used together with the APEX 20K Programmable Logic Device Family Data Sheet.

Altera Corporation

Excalibur Device Overview

Table Excalibur Device Overview

Processor Maximum operating frequency Single-port SRAM Dual-port SRAM Typical gates Logic elements LEs Embedded system blocks ESBs Maximum system gates

Maximum user I/Os 1

UART, timer, watchdog timer JTAG debug module Embedded trace module General purpose I/O Port Low-power PLL

EPXA1

ARM922T 200 MHz 32 Kbytes 16 Kbytes 100,000
4,160 26
263,000 246 Yes 4 bits Yes

Note 1 Maximum available user I/Os = shared stripe I/O + PLD I/O

EPXA4

ARM922T 200 MHz 128 Kbytes 64 Kbytes 400,000 16,640
104 1,052,000
488 Yes 8 bits

EPXA10

ARM922T 200 MHz 256 Kbytes 128 Kbytes 1,000,000 38,400

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Datasheet ID: EPXA1F484C2 517138