EP20K1000CF33C7N

EP20K1000CF33C7N Datasheet

EP20K200C

Part	Datasheet
EP20K1000CF33C7N	EP20K1000CF33C7N (pdf)

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EP20K1000CB652C7N	EP20K1000CB652C7N
EP20K1000CB652C8N	EP20K1000CB652C8N
EP20K1000CB652C8ES	EP20K1000CB652C8ES
EP20K200CF484C8ES	EP20K200CF484C8ES
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EP20K200CQ240C7ES	EP20K200CQ240C7ES
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EP20K1000CB652C9N	EP20K1000CB652C9N
EP20K200CQ208C7ES	EP20K200CQ208C7ES
EP20K200CF672C9	EP20K200CF672C9
EP20K200CF672C8ES	EP20K200CF672C8ES
EP20K200CF672C8	EP20K200CF672C8
EP20K200CF672C7	EP20K200CF672C7
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EP20K200CB652C7ES	EP20K200CB652C7ES
EP20K200CB652C7	EP20K200CB652C7
EP20K1000CF672C8ES	EP20K1000CF672C8ES
EP20K400CB652C9ES	EP20K400CB652C9ES
EP20K1000CF33C9N	EP20K1000CF33C9N
EP20K1000CF672C7GZ	EP20K1000CF672C7GZ
EP20K200CF672C7ES	EP20K200CF672C7ES

PDF Datasheet Preview
February 2004 ver. APEX 20KC Programmable Logic Device Data Sheet Features... • Programmable logic device PLD manufactured using a 0.15-µm alllayer copper-metal fabrication process 25 to 35% faster design performance than APEXTM 20KE devices Pin-compatible with APEX 20KE devices High-performance, low-power copper interconnect MultiCoreTM architecture integrating look-up table LUT logic and embedded memory LUT logic used for register-intensive functions Embedded system blocks ESBs used to implement memory functions, including first-in first-out FIFO buffers, dual-port RAM, and content-addressable memory CAM • High-density architecture 200,000 to 1 million typical gates see Table 1 Up to 38,400 logic elements LEs Up to 327,680 RAM bits that can be used without reducing available logic Table APEX 20KC Device Features Note 1 EP20K200C EP20K400C EP20K600C EP20K1000C Maximum system gates Typical gates LEs ESBs Maximum RAM bits PLLs 2 Speed grades 3 Maximum macrocells Maximum user I/O pins 526,000 200,000 8,320 52 106,496 2 -7, -8, -9 832 376 1,052,000 400,000 16,640 104 212,992 4 -7, -8, -9 1,664 488 1,537,000 600,000 24,320 152 311,296 4 -7, -8, -9 2,432 588 1,772,000 1,000,000 38,400 160 327,680 4 -7, -8, -9 2,560 708 Notes to Table 1 The embedded IEEE Std. Joint Test Action Group JTAG boundary-scan circuitry contributes up to 57,000 additional gates. 2 PLL phase-locked loop. 3 The -7 speed grade provides the fastest performance. Altera Corporation DS-APEX20KC-2.2 APEX 20KC Programmable Logic Device Data Sheet ...and More Features • Low-power operation design 1.8-V supply voltage see Table 2 Copper interconnect reduces power consumption MultiVoltTM I/O support for 1.8-V, 2.5-V, and 3.3-V interfaces ESBs offering programmable power-saving mode • Flexible clock management circuitry with up to four phase-locked loops PLLs Built-in low-skew clock tree Up to eight global clock signals ClockLockTM feature reducing clock delay and skew ClockBoostTM feature providing clock multiplication and division ClockShiftTM feature providing programmable clock phase and delay shifting Table APEX 20KC Supply Voltages Voltage Internal supply voltage VCCINT MultiVolt I/O interface voltage levels VCCIO V, V, V, V 1 Ordering Information Figure 39 describes the ordering codes for Stratix devices. For more information on a specific package, refer to the Altera Device Package Information Data Sheet. Altera Corporation APEX 20KC Programmable Logic Device Data Sheet Figure APEX 20KC Device Packaging Ordering Information Family Signature EP20K APEX 20K Device Type 200C 400C 600C 1000C EP20K 1000C F 1020 ES Optional Suffix Indicates specific device options or shipment method. ES Engineering sample Speed Grade 7, 8, or 9, with 7 being the fastest Package Type Q Plastic quad flat package PQFP B Ball-grid array BGA F FineLine BGA Operating Temperature Pin Count C Commercial temperature tJ = C to C I Industrial temperature tJ = C to C Number of pins for a particular package The information contained in the APEX 20KC Programmable Logic Device Data Sheet version supersedes information published in previous versions. Version The following changes were made to the APEX 20KC Programmable Logic Device Data Sheet version • Updated Tables • Updated notes in Tables Version The following changes were made to the APEX 20KC Programmable Logic Device Data Sheet version • Removed figure on AC Test Conditions. • Updated conditions in Tables 40 and • Added Tables 42 and • Updated VOD in Table • Added Figures 36 through • Updated Tables 44 through • Updated Tables 62 through • Removed notes in Tables 44 through • Various textual changes throughout the document. Altera Corporation APEX 20KC Programmable Logic Device Data Sheet Altera Corporation APEX 20KC Programmable Logic Device Data Sheet 101 Innovation Drive San Jose, CA 95134 408 544-7000 Applications Hotline 800-EPLD Customer Marketing 408 544-7104 Literature Services: Copyright 2002 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, mask work rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. Altera Corporation

PDF Datasheet Preview

February 2004 ver.

APEX 20KC

Programmable Logic Device

Data Sheet

Features...
• Programmable logic device PLD manufactured using a 0.15-µm alllayer copper-metal fabrication process 25 to 35% faster design performance than APEXTM 20KE devices Pin-compatible with APEX 20KE devices High-performance, low-power copper interconnect MultiCoreTM architecture integrating look-up table LUT logic and embedded memory LUT logic used for register-intensive functions Embedded system blocks ESBs used to implement memory functions, including first-in first-out FIFO buffers, dual-port RAM, and content-addressable memory CAM
• High-density architecture 200,000 to 1 million typical gates see Table 1 Up to 38,400 logic elements LEs Up to 327,680 RAM bits that can be used without reducing available logic

Table APEX 20KC Device Features Note 1

EP20K200C

EP20K400C

EP20K600C

EP20K1000C

Maximum system gates Typical gates LEs ESBs Maximum RAM bits PLLs 2 Speed grades 3 Maximum macrocells Maximum user I/O pins
526,000 200,000
8,320 52
106,496 2
-7, -8, -9 832 376
1,052,000 400,000 16,640
104 212,992
4 -7, -8, -9
1,664 488
1,537,000 600,000 24,320
152 311,296
4 -7, -8, -9
2,432 588
1,772,000 1,000,000
38,400 160
327,680 4
-7, -8, -9 2,560 708

Notes to Table 1 The embedded IEEE Std. Joint Test Action Group JTAG boundary-scan circuitry contributes up to
57,000 additional gates. 2 PLL phase-locked loop. 3 The -7 speed grade provides the fastest performance.

Altera Corporation

DS-APEX20KC-2.2

APEX 20KC Programmable Logic Device Data Sheet
...and More Features
• Low-power operation design 1.8-V supply voltage see Table 2 Copper interconnect reduces power consumption MultiVoltTM I/O support for 1.8-V, 2.5-V, and 3.3-V interfaces ESBs offering programmable power-saving mode
• Flexible clock management circuitry with up to four phase-locked loops PLLs Built-in low-skew clock tree Up to eight global clock signals ClockLockTM feature reducing clock delay and skew ClockBoostTM feature providing clock multiplication and division ClockShiftTM feature providing programmable clock phase and delay shifting

Table APEX 20KC Supply Voltages

Voltage

Internal supply voltage VCCINT

MultiVolt I/O interface voltage levels VCCIO V, V, V, V 1
Ordering Information
Figure 39 describes the ordering codes for Stratix devices. For more information on a specific package, refer to the Altera Device Package Information Data Sheet.

Altera Corporation

APEX 20KC Programmable Logic Device Data Sheet
Figure APEX 20KC Device Packaging Ordering Information

Family Signature EP20K APEX 20K

Device Type 200C 400C 600C 1000C

EP20K 1000C F
1020

ES Optional Suffix

Indicates specific device options or shipment method. ES Engineering sample

Speed Grade 7, 8, or 9, with 7 being the fastest

Package Type

Q Plastic quad flat package PQFP B Ball-grid array BGA F FineLine BGA

Operating Temperature

Pin Count

C Commercial temperature tJ = C to C I Industrial temperature tJ = C to C

Number of pins for a particular package

The information contained in the APEX 20KC Programmable Logic Device Data Sheet version supersedes information published in previous versions.

Version

The following changes were made to the APEX 20KC Programmable Logic Device Data Sheet version
• Updated Tables
• Updated notes in Tables

Version

The following changes were made to the APEX 20KC Programmable Logic Device Data Sheet version
• Removed figure on AC Test Conditions.
• Updated conditions in Tables 40 and
• Added Tables 42 and
• Updated VOD in Table
• Added Figures 36 through
• Updated Tables 44 through
• Updated Tables 62 through
• Removed notes in Tables 44 through
• Various textual changes throughout the document.

Altera Corporation

APEX 20KC Programmable Logic Device Data Sheet

Altera Corporation

APEX 20KC Programmable Logic Device Data Sheet
101 Innovation Drive San Jose, CA 95134 408 544-7000 Applications Hotline 800-EPLD Customer Marketing 408 544-7104 Literature Services:

Copyright 2002 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, mask work rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

Altera Corporation

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Datasheet ID: EP20K1000CF33C7N 517128