EP20K100FC144-1

EP20K100FC144-1 Datasheet


EP20K30E EP20K60E

Part Datasheet
EP20K100FC144-1 EP20K100FC144-1 EP20K100FC144-1 (pdf)
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PDF Datasheet Preview
March 2004, ver.

APEX 20K

Programmable Logic Device Family

Data Sheet
• Industry’s first programmable logic device PLD incorporating system-on-a-programmable-chip SOPC integration MultiCoreTM architecture integrating look-up table LUT logic, product-term logic, and embedded memory LUT logic used for register-intensive functions Embedded system block ESB used to implement memory functions, including first-in first-out FIFO buffers, dual-port RAM, and content-addressable memory CAM ESB implementation of product-term logic used for combinatorial-intensive functions
• High density 30,000 to million typical gates see Tables 1 and 2 Up to 51,840 logic elements LEs Up to 442,368 RAM bits that can be used without reducing available logic Up to 3,456 product-term-based macrocells

Table APEX 20K Device Features Note 1

Maximum system gates Typical gates LEs ESBs Maximum RAM bits Maximum macrocells Maximum user I/O pins

EP20K30E EP20K60E
113,000 162,000
30,000
1,200 12
24,576
60,000
2,560 16
32,768

EP20K100
263,000
100,000 4,160 26 53,248 416 252

EP20K100E EP20K160E
263,000
404,000
100,000
4,160 26
53,248
160,000
6,400 40
81,920

EP20K200
526,000
200,000 8,320 52
106,496 832 382

EP20K200E
526,000
200,000 8,320 52
106,496 832 376

Altera Corporation

DS-APEX20K-5.1

APEX 20K Programmable Logic Device Family Data Sheet

Table Additional APEX 20K Device Features Note 1

Maximum system gates Typical gates LEs ESBs Maximum RAM bits Maximum macrocells Maximum user I/O pins
The APEX 20KE device contains eight I/O banks. In QFP packages, the banks are linked to form four I/O banks. The I/O banks directly support all standards except LVDS and LVPECL. All I/O banks can support LVDS and LVPECL with the addition of external resistors. In addition, one block within a bank contains circuitry to support high-speed True-LVDS and LVPECL inputs, and another block within a particular bank supports high-speed True-LVDS and LVPECL outputs. The LVDS blocks support all of the I/O standards. Each I/O bank has its own VCCIO pins. A single device can support 1.8-V, 2.5-V, and 3.3-V interfaces each bank can support a different standard independently. Each bank can also use a separate VREF level so that each bank can support any of the terminated standards such as SSTL-3 independently. Within a bank, any one of the terminated standards can be supported. EP20K300E and larger APEX 20KE devices support the LVDS interface for data pins smaller devices support LVDS clock pins, but not data pins . All EP20K300E and larger devices support the LVDS interface for data pins up to 155 Mbit per channel EP20K400E devices and larger with an X-suffix on the ordering code add a serializer/deserializer circuit and PLL for higher-speed support.

Each bank can support multiple standards with the same VCCIO for output pins. Each bank can support one voltage-referenced I/O standard, but it can support multiple I/O standards with the same VCCIO voltage level. For example, when VCCIO is V, a bank can support LVTTL, LVCMOS, 3.3-V PCI, and SSTL-3 for inputs and outputs.

When the LVDS banks are not used as LVDS I/O banks, they support all of the other I/O standards. Figure 29 shows the arrangement of the APEX 20KE I/O banks.

Altera Corporation

APEX 20K Programmable Logic Device Family Data Sheet

Figure APEX 20KE I/O Banks

I/O Bank 1

I/O Bank 2

I/O Bank 8

LVDS/LVPECL Output Block 2
1 I/O Bank 7

Regular I/O Blocks Support
• LVTTL
• LVCMOS
• V
• V
• V PCI
• LVPECL
• HSTL Class I
• GTL+
• SSTL-2 Class I and II
• SSTL-3 Class I and II
• CTT
• AGP

Individual Power Bus

I/O Bank 3 1 LVDS/LVPECL Input Block 2

I/O Bank 4

I/O Bank 6

I/O Bank 5

Notes to Figure 29 1 For more information on placing I/O pins in LVDS blocks, refer to the Guidelines for

Using LVDS Blocks section in Application Note 120 Using LVDS in APEX 20KE Devices . 2 If the LVDS input and output blocks are not used for LVDS, they can support all of the I/O standards and can be used as input, output, or bidirectional pins with VCCIO set to V, V, or V.

Power Sequencing & Hot Socketing

Because APEX 20K and APEX 20KE devices can be used in a mixedvoltage environment, they have been designed specifically to tolerate any possible power-up sequence. Therefore, the VCCIO and VCCINT power supplies may be powered in any order.

For more information, please refer to the “Power Sequencing Considerations” section in the Configuring APEX 20KE & APEX 20KC Devices chapter of the Configuration Devices Handbook.

Signals can be driven into APEX 20K devices before and during power-up without damaging the device. In addition, APEX 20K devices do not drive out during power-up. Once operating conditions are reached and the device is configured, APEX 20K and APEX 20KE devices operate as specified by the user.

Altera Corporation

APEX 20K Programmable Logic Device Family Data Sheet

MultiVolt I/O Interface

Under hot socketing conditions, APEX 20KE devices will not sustain any damage, but the I/O pins will drive out.

The APEX device architecture supports the MultiVolt I/O interface feature, which allows APEX devices in all packages to interface with systems of different supply voltages. The devices have one set of VCC pins for internal operation and input buffers VCCINT , and another set for I/O output drivers VCCIO .

The APEX 20K VCCINT pins must always be connected to a V power supply. With a 2.5-V VCCINT level, input pins are 2.5-V, 3.3-V, and 5.0-V tolerant. The VCCIO pins can be connected to either a 2.5-V or 3.3-V power supply, depending on the output requirements. When VCCIO pins are connected to a 2.5-V power supply, the output levels are compatible with 2.5-V systems. When the VCCIO pins are connected to a 3.3-V power supply, the output high is V and is compatible with 3.3-V or 5.0-V systems.

Table 12 summarizes 5.0-V tolerant APEX 20K MultiVolt I/O support.

Table 5.0-V Tolerant APEX 20K MultiVolt I/O Support

VCCIO V

Input Signals V

Output Signals V

Notes to Table 12:
1 The PCI clamping diode must be disabled to drive an input with voltages higher
than VCCIO. 2 When VCCIO = V, an APEX 20K device can drive a 2.5-V device with 3.3-V
tolerant inputs.

Open-drain output pins on 5.0-V tolerant APEX 20K devices with a pull-
up resistor to the 5.0-V supply can drive 5.0-V CMOS input pins that
require a VIH of V. When the pin is inactive, the trace will be pulled up to V by the resistor. The open-drain pin will only drive low or tri-state;
APEX 20K devices support the ClockLock and ClockBoost clock management features, which are implemented with PLLs. The ClockLock circuitry uses a synchronizing PLL that reduces the clock delay and skew within a device. This reduction minimizes clock-to-output and setup times while maintaining zero hold times. The ClockBoost circuitry, which provides a clock multiplier, allows the designer to enhance device area efficiency by sharing resources within the device. The ClockBoost circuitry allows the designer to distribute a low-speed clock and multiply that clock on-device. APEX 20K devices include a high-speed clock tree unlike ASICs, the user does not have to design and optimize the clock tree. The ClockLock and ClockBoost features work in conjunction with the APEX 20K device’s high-speed clock to provide significant improvements in system performance and band-width. Devices with an X-suffix on the ordering code include the ClockLock circuit.

The ClockLock and ClockBoost features in APEX 20K devices are enabled through the Quartus II software. External devices are not required to use these features.

Altera Corporation

APEX 20K Programmable Logic Device Family Data Sheet

For designs that require both a multiplied and non-multiplied clock, the clock trace on the board can be connected to CLK2p. Table 14 shows the combinations supported by the ClockLock and ClockBoost circuitry. The CLK2p pin can feed both the ClockLock and ClockBoost circuitry in the APEX 20K device. However, when both circuits are used, the other clock pin CLK1p cannot be used.

Table Multiplication Factor Combinations

Clock 1
x1, x2 x1, x2, x4

Clock 2
x1 x2 x4

APEX 20KE ClockLock Feature

APEX 20KE devices include an enhanced ClockLock feature set. These devices include up to four PLLs, which can be used independently. Two PLLs are designed for either general-purpose use or LVDS use on devices that support LVDS I/O pins . The remaining two PLLs are designed for general-purpose use. The EP20K200E and smaller devices have two PLLs the EP20K300E and larger devices have four PLLs.

The following sections describe some of the features offered by the APEX 20KE PLLs.

External PLL Feedback

The ClockLock circuit’s output can be driven off-chip to clock other devices in the system further, the feedback loop of the PLL can be routed off-chip. This feature allows the designer to exercise fine control over the I/O interface between the APEX 20KE device and another high-speed device, such as SDRAM.

Clock Multiplication

The APEX 20KE ClockBoost circuit can multiply or divide clocks by a programmable number. The clock can be multiplied by m/ n x k or m/ n x v , where m and k range from 2 to 160, and n and v range from 1 to Clock multiplication and division can be used for time-domain multiplexing and other functions, which can reduce design LE requirements.

Altera Corporation

APEX 20K Programmable Logic Device Family Data Sheet

Clock Phase & Delay Adjustment

The APEX 20KE ClockShift feature allows the clock phase and delay to be adjusted. The clock phase can be adjusted by 90° steps. The clock delay can be adjusted to increase or decrease the clock delay by an arbitrary amount, up to one clock period.

LVDS Support

Two PLLs are designed to support the LVDS interface. When using LVDS, the I/O clock runs at a slower rate than the data transfer rate. Thus, PLLs are used to multiply the I/O clock internally to capture the LVDS data. For example, an I/O clock may run at 105 MHz to support 840 megabits per second Mbps LVDS data transfer. In this example, the PLL multiplies the incoming clock by eight to support the high-speed data transfer. You can use PLLs in EP20K400E and larger devices for high-speed LVDS interfacing.

Lock Signals

The APEX 20KE ClockLock circuitry supports individual LOCK signals. The LOCK signal drives high when the ClockLock circuit has locked onto the input clock. The LOCK signals are optional for each ClockLock circuit when not used, they are I/O pins.

ClockLock & ClockBoost Timing Parameters

For the ClockLock and ClockBoost circuitry to function properly, the incoming clock must meet certain requirements. If these specifications are not met, the circuitry may not lock onto the incoming clock, which generates an erroneous clock within the device. The clock generated by the ClockLock and ClockBoost circuitry must also meet certain specifications. If the incoming clock meets these requirements during configuration, the APEX 20K ClockLock and ClockBoost circuitry will lock onto the clock during configuration. The circuit will be ready for use immediately after configuration. In APEX 20KE devices, the clock input standard is programmable, so the PLL cannot respond to the clock until the device is configured. The PLL locks onto the input clock as soon as configuration is complete. Figure 30 shows the incoming and generated clock specifications.
1 For more information on ClockLock and ClockBoost circuitry, see Application Note 115 Using the ClockLock and ClockBoost PLL Features in APEX Devices.

Altera Corporation

APEX 20K Programmable Logic Device Family Data Sheet

Figure Specifications for the Incoming & Generated Clocks Note 1
f CLK1,f CLK2, f CLK4
t INDUTY
t I + t CLKDEV

Input Clock
t OUTDUTY
t I + t INCLKSTB

ClockLock Generated Clock
tO + t JITTER tO t JITTER

Note to Figure 30 1 The tI parameter refers to the nominal input clock period the tO parameter refers
to the nominal output clock period.
More datasheets: EP20K100BC356-3V | EP20K100BI356-3 | EP20K100EF324I2XGZ | EP20K100EFC324-3GZ | EP20K100EFI144-2N | EP20K100EFI144-3 | EP20K100EFI324-3 | EP20K100EQI208-3 | EP20K100EQI240-3 | EP20K100ETI144-3


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Datasheet ID: EP20K100FC144-1 517126