AS4C8M16S-6TINTR
AS4C8M16S-6TINTR Datasheet
AS4C8M16S
| Part | Datasheet |
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AS4C8M16S-6TINTR |
AS4C8M16S-6TINTR (pdf) |
| Related Parts | Information |
|---|---|
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AS4C8M16S-6TIN |
AS4C8M16S-6TIN |
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AS4C8M16S-7TCN |
AS4C8M16S-7TCN |
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AS4C8M16S-6TCNTR |
AS4C8M16S-6TCNTR |
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AS4C8M16S-6TAN |
AS4C8M16S-6TAN |
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AS4C8M16S-7TCNTR |
AS4C8M16S-7TCNTR |
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AS4C8M16S-6TANTR |
AS4C8M16S-6TANTR |
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AS4C8M16S-6TCN |
AS4C8M16S-6TCN |
| PDF Datasheet Preview |
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| FEBRUARY 2011 AS4C8M16S Alliance Memory 128Mb/ 8M x 16 bit Synchronous DRAM SDRAM • Fast access time from clock ns • Fast clock rate 166/143 MHz • Fully synchronous operation • Internal pipelined architecture • 2M word x 16-bit x 4-bank • Programmable Mode registers - CAS Latency 2, or 3 - Burst Length 1, 2, 4, 8, or full page - Burst Type interleaved or linear burst - Burst stop function • Auto Refresh and Self Refresh • 4096 refresh cycles/64ms • CKE power down mode • Single +3.3V ± 0.3V power supply • Interface LVTTL • 54-pin 400 mil plastic TSOP II package - Pb free and Halogen free Table1. Key Specifications AS4C8M16S tCK3 Clock Cycle time min. tAC3 Access time from CLK max. tRAS Row Active time min. tRC Row Cycle time min. - 6/7 6/7ns 5/5.4ns 42/42ns 60/63ns Table Ordering Information Frequency AS4C8M16S -6TAN 166MHz AS4C8M16S-6TIN 166MHz AS4C8M16S -7TCN 143MHz Package TSOP II TSOP II TSOP II T indicates TSOPII Package, N indicates Pb and Halogen Free for TSOPII Package Figure Pin Assignment Top View Overview The AS4C8M16S SDRAM is a high-speed CMOS synchronous DRAM containing 128 Mbits. It is internally configured as 4 Banks of 2M word x 16 DRAM with a synchronous interface all signals are registered on the positive edge of the clock signal, CLK . Read and write accesses to the SDRAM are burst oriented accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command. The AS4C8M16S provides for programmable Read or Write burst lengths of 1, 2, 4, 8, or full page, with a burst termination option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy to use. By having a programmable mode register, the system can choose the most suitable modes to maximize its performance. These devices are well suited for applications requiring high memory bandwidth and particularly well suited to high performance PC applications. VDDQ VSSQ VDDQ VSSQ LDQM CAS# RAS# A10/AP DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 VDDQ NC/RFU UDQM FEBRUARY 2011 Figure Block Diagram CS# RAS# CAS# WE# BUFFER COMMAND DECODER CONTROL SIGNAL GENERATOR A10/AP A0 A9 A11 BA0 BA1 ORDERING INFORMATION Alliance AS4C8M16S-6TAN AS4C8M16S-6TIN AS4C8M16S-7TCN Organization VCC Range Package 8M x 16 3.3V+/-0.3V 54 TSOP II 8M x 16 8M x 16 3.3V+/-0.3V 54 TSOP II 3.3V+/-0.3V 54 TSOP II Operating Temp Automotive Industrial Commercial Speed MHz 166 143 PART NUMBERING SYSTEM AS4C 8M146MS4 S= SDRAM prefix 128Mb 8Mx16 -7 Speed T=TSOP Package 54 pin TSOP II Temperature Range C = Commercial 0 - 70°C I = Industrial -45 - 85°C A = Automotive -45 - 105°C N = Lead Free RoHS compliant part |
| More datasheets: T48C862M-R3-TNS | T48C862M-R3-TNQ | DM-4 | ATR2434-PLT | 255 | AS4C8M16S-6TIN | AS4C8M16S-7TCN | AS4C8M16S-6TCNTR | AS4C8M16S-6TAN | AS4C8M16S-7TCNTR |
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