AS4C32M16D3L-12BCN

AS4C32M16D3L-12BCN Datasheet

AS4C32M16D3L-12BIN AS4C32M16D3L-12BCN

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AS4C32M16D3L-12BIN	AS4C32M16D3L-12BIN

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AS4C32M16D3L-12BIN AS4C32M16D3L-12BCN Date Sep. 2017 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL 650 610-6800 FAX 650 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice Confidential - 1 of 86 - AS4C32M16D3L-12BIN AS4C32M16D3L-12BCN 32M x 16 bit DDR3L Synchronous DRAM SDRAM JEDEC Standard Compliant Power supplies VDD & VDDQ = +1.35V 1.283V ~ 1.45V Backward compatible to VDD & VDDQ = +1.5V ±0.075V temperature: - Commercial TC = 0~95°C - Industrial TC = -40~95°C Supports JEDEC clock jitter specification Fully synchronous operation clock rate 800MHz Differential Clock, CK & CK# Bidirectional differential data strobe - DQS & DQS# 8 internal banks for concurrent operation 8n-bit prefetch architecture Pipelined internal architecture Precharge & active power down Programmable Mode & Extended Mode registers Additive Latency AL 0, CL-1, CL-2 Programmable Burst lengths 4, 8 Burst type Sequential / Interleave Output Driver Impedance Control Average refresh period - 8192 cycles/64ms 7.8us at -40°C TC +85°C - 8192 cycles/32ms 3.9us at +85°C TC +95°C Write Leveling ZQ Calibration Dynamic ODT Rtt_Nom & Rtt_WR RoHS compliant Auto Refresh and Self Refresh 96-ball 8 x 13 x 1.0mm FBGA package - Pb and Halogen Free Overview The 512Mb Double-Data-Rate-3L DDR3L DRAMs is double data rate architecture to achieve high-speed operation. It is internally configured as an eight bank DRAM. The 512Mb chip is organized as 4Mbit x 16 I/Os x 8 bank devices. These synchronous devices achieve high speed double-data-rate transfer rates of up to 1600 Mb /sec/pin for general applications. The chip is designed to comply with all key DDR3L DRAM key features and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks CK rising and CK# falling . All I/Os are synchronized with differential DQS pair in a source synchronous fashion. These devices operate with a single 1.35V -0.067V / +0.1V power supply and are available in BGA packages. Table Ordering Information Product part No Temperature Max Clock MHz AS4C32M16D3L-12BCN 32M x 16 Commercial 0°C to 95°C AS4C32M16D3L-12BIN 32M x 16 Industrial -40°C to 95°C Package 96-ball FBGA 96-ball FBGA Table Speed Grade Information Speed Grade Clock Frequency CAS Latency DDR3-1600 800 MHz tRCD ns tRP ns Confidential - 2 of 86 - AS4C32M16D3L-12BIN AS4C32M16D3L-12BCN Figure Ball Assignment FBGA Top View A VDDQ DQ13 DQ15 DQ12 VDDQ VSS B VSSQ VDD C VDDQ DQ11 UDQS#. UDQS DQ14 DQ10 VSSQ VDDQ D VSSQ VDDQ UDM DQ8 VSSQ VDD VSSQ LDM VSSQ VDDQ VDDQ LDQS DQ3 VSSQ VSSQ LDQS# VSS VSSQ H VREFDQ VDDQ DQ5 VDDQ VSS RAS# K ODT VDD CAS# A10/AP ZQ Accesses within a given burst may be programmed to sequential or interleaved order. The burst type is selected via bit A3 as shown in the MR0 Definition as above figure. The ordering of access within a burst is determined by the burst length, burst type, and the starting column address. The burst length is defined by bits A0-A1. Burst lengths options include fix BC4, fixed BL8, and on the fly which allow BC4 or BL8 to be selected coincident with the registration of a Read or Write command via A12/BC# Table Burst Type and Burst Order Burst Length Read Write Starting Column Address A2 A1 A0 Sequential A3=0 Interleave A3=1 Note 0, 1, 2, 3, T, T, T, T 0, 1, 2, 3, T, T, T, T 0 1, 2, 3, 0, T, T, T, T 1, 0, 3, 2, T, T, T, T 0 1 0 2, 3, 0, 1, T, T, T, T 2, 3, 0, 1, T, T, T, T 4 Chop Read 3, 0, 1, 2, T, T, T, T 3, 2, 1, 0, T, T, T, T 4, 5, 6, 7, T, T, T, T 4, 5, 6, 7, T, T, T, T 1, 2, 3 1 0 1 5, 6, 7, 4, T, T, T, T 5, 4, 7, 6, T, T, T, T 1 0 6, 7, 4, 5, T, T, T, T 6, 7, 4, 5, T, T, T, T 1 7, 4, 5, 6, T, T, T, T 7, 6, 5, 4, T, T, T, T Write 0, 1, 2, 3, X, X, X, X 4, 5, 6, 7, X, X, X, X 0, 1, 2, 3, X, X, X, X 4, 5, 6, 7, X, X, X, X 1, 2, 4, 5 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 0 1, 2, 3, 0, 5, 6, 7, 4 1, 0, 3, 2, 5, 4, 7, 6 0 1 0 2, 3, 0, 1, 6, 7, 4, 5 2, 3, 0, 1, 6, 7, 4, 5 Read 0 1 3, 0, 1, 2, 7, 4, 5, 6 3, 2, 1, 0, 7, 6, 5, 4 1 0 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 1 0 1 5, 6, 7, 4, 1, 2, 3, 0 5, 4, 7, 6, 1, 0, 3, 2 1 0 6, 7, 4, 5, 2, 3, 0, 1 6, 7, 4, 5, 2, 3, 0, 1 1 7, 4, 5, 6, 3, 0, 1, 2 7, 6, 5, 4, 3, 2, 1, 0 Write V 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 2, 4 Note In case of burst length being fixed to 4 by MR0 setting, the internal write operation starts two clock cycles earlier than for the BL8 mode. This means that the starting point for tWR and tWTR will be pulled in by two clocks. In case of burst length being selected on-the-fly via A12/BC#, the internal write operation starts at the same point in time like a burst of 8 write operation. This means that during on-the-fly control, the starting point for tWR and tWTR will not be pulled in by two clocks. Note 0~7 bit number is value of CA[2:0] that causes this bit to be the first read during a burst. Note T Output driver for data and strobes are in high impedance. Note V a valid logic level 0 or 1 , but respective buffer input ignores level on input pins. Note X Don’t Care. - DLL Reset The DLL Reset bit is self-clearing, meaning it returns back to the value of ‘0’ after the DLL reset function has been issued. Once the DLL is enabled, a subsequent DLL Reset should be applied. Anytime the DLL reset function is used, tDLLK must be met before any functions that require the DLL can be used i.e. Read commands or ODT synchronous operations. - Write Recovery The programmed WR value MR0 bits A9, A10, and A11 is used for the auto precharge feature along with tRP to determine tDAL. WR write recovery for auto-precharge min in clock cycles is calculated by dividing tWR ns by tCK ns and rounding up to the next integer WR min [cycles] = Roundup tWR [ns]/tCK [ns] . The WR must be programmed to be equal or larger than tWR min . burst order is switched on nibble base A [2]=0b, Burst order 0,1,2,3 * A[2]=1b, Burst order 4,5,6,7 * A[9:3] don’t care A10/AP don’t care A12/BC Selects burst chop mode on-the-fly, if enabled within MR0. A11 if available don’t care Regular interface functionality during register reads Support two Burst Ordering which are switched with A2 and A[1:0]=00b. Support of read burst chop MRS and on-the-fly via A12/BC All other address bits remaining column address bits including A10, all bank address bits will be ignored by the DDR3L SDRAM. Regular read latencies and AC timings apply. DLL must be locked prior to MPR Reads. NOTE * Burst order bit 0 is assigned to LSB and burst order bit 7 is assigned to MSB of the selected MPR agent. Table MPR MR3 Register Definition MR3 A[2] MR3 A[1:0] Function Burst Length Read Predefined Pattern for System Calibration Read Address A[2:0] Burst Order and Data Pattern 000b Burst order 0, 1, 2, 3, 4, 5, 6, 7 Pre-defined Data Pattern [0, 1, 0, 1, 0, 1, 0, 1] 000b Burst order 0, 1, 2, 3 Pre-defined Data Pattern [0, 1, 0, 1] 100b Burst order 4, 5, 6, 7 Pre-defined Data Pattern [0, 1, 0, 1] 000b Burst order 0, 1, 2, 3, 4, 5, 6, 7 000b Burst order 0, 1, 2, 3 100b Burst order 4, 5, 6, 7 000b Burst order 0, 1, 2, 3, 4, 5, 6, 7 000b Burst order 0, 1, 2, 3 100b Burst order 4, 5, 6, 7 000b Burst order 0, 1, 2, 3, 4, 5, 6, 7 000b Burst order 0, 1, 2, 3

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AS4C32M16D3L-12BIN AS4C32M16D3L-12BCN

Date Sep. 2017

Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL 650 610-6800 FAX 650 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice

Confidential
- 1 of 86 -

AS4C32M16D3L-12BIN AS4C32M16D3L-12BCN
32M x 16 bit DDR3L Synchronous DRAM SDRAM

JEDEC Standard Compliant Power supplies VDD & VDDQ = +1.35V 1.283V ~ 1.45V Backward compatible to VDD & VDDQ = +1.5V ±0.075V
temperature:
- Commercial TC = 0~95°C - Industrial TC = -40~95°C

Supports JEDEC clock jitter specification Fully synchronous operation clock rate 800MHz Differential Clock, CK & CK# Bidirectional differential data strobe
- DQS & DQS# 8 internal banks for concurrent operation 8n-bit prefetch architecture Pipelined internal architecture Precharge & active power down Programmable Mode & Extended Mode registers Additive Latency AL 0, CL-1, CL-2 Programmable Burst lengths 4, 8 Burst type Sequential / Interleave Output Driver Impedance Control Average refresh period
- 8192 cycles/64ms 7.8us at -40°C TC +85°C - 8192 cycles/32ms 3.9us at +85°C TC +95°C Write Leveling ZQ Calibration Dynamic ODT Rtt_Nom & Rtt_WR RoHS compliant Auto Refresh and Self Refresh 96-ball 8 x 13 x 1.0mm FBGA package - Pb and Halogen Free

Overview

The 512Mb Double-Data-Rate-3L DDR3L DRAMs is double data rate architecture to achieve high-speed operation. It is internally configured as an eight bank DRAM.

The 512Mb chip is organized as 4Mbit x 16 I/Os x 8 bank devices. These synchronous devices achieve high speed double-data-rate transfer rates of up to 1600 Mb /sec/pin for general applications.

The chip is designed to comply with all key DDR3L DRAM key features and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks CK rising and CK# falling . All I/Os are synchronized with differential DQS pair in a source synchronous fashion.

These devices operate with a single 1.35V -0.067V / +0.1V power supply and are available in BGA packages.
Table Ordering Information

Product part No

Temperature

Max Clock MHz

AS4C32M16D3L-12BCN 32M x 16 Commercial 0°C to 95°C

AS4C32M16D3L-12BIN 32M x 16 Industrial -40°C to 95°C

Package 96-ball FBGA 96-ball FBGA

Table Speed Grade Information

Speed Grade

Clock Frequency CAS Latency

DDR3-1600
800 MHz
tRCD ns
tRP ns

Confidential
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AS4C32M16D3L-12BIN AS4C32M16D3L-12BCN

Figure Ball Assignment FBGA Top View

A VDDQ DQ13 DQ15

DQ12 VDDQ VSS

B VSSQ VDD

C VDDQ DQ11

UDQS#. UDQS

DQ14 DQ10

VSSQ VDDQ

D VSSQ VDDQ UDM

DQ8 VSSQ VDD

VSSQ

LDM VSSQ VDDQ

VDDQ

LDQS

DQ3 VSSQ

VSSQ

LDQS#

VSS VSSQ

H VREFDQ VDDQ

DQ5 VDDQ

VSS RAS#

K ODT

VDD CAS#

A10/AP ZQ
Accesses within a given burst may be programmed to sequential or interleaved order. The burst type is selected via bit A3 as shown in the MR0 Definition as above figure. The ordering of access within a burst is determined by the burst length, burst type, and the starting column address. The burst length is defined by bits A0-A1. Burst lengths options include fix BC4, fixed BL8, and on the fly which allow BC4 or BL8 to be selected coincident with the registration of a Read or Write command via A12/BC#

Table Burst Type and Burst Order

Burst Length

Read Write

Starting Column Address

A2 A1 A0

Sequential A3=0

Interleave A3=1

Note
0, 1, 2, 3, T, T, T, T 0, 1, 2, 3, T, T, T, T
0 1, 2, 3, 0, T, T, T, T 1, 0, 3, 2, T, T, T, T
0 1 0 2, 3, 0, 1, T, T, T, T 2, 3, 0, 1, T, T, T, T
4 Chop

Read
3, 0, 1, 2, T, T, T, T 3, 2, 1, 0, T, T, T, T 4, 5, 6, 7, T, T, T, T 4, 5, 6, 7, T, T, T, T
1, 2, 3
1 0 1 5, 6, 7, 4, T, T, T, T 5, 4, 7, 6, T, T, T, T
1 0 6, 7, 4, 5, T, T, T, T 6, 7, 4, 5, T, T, T, T
1 7, 4, 5, 6, T, T, T, T 7, 6, 5, 4, T, T, T, T

Write
0, 1, 2, 3, X, X, X, X 4, 5, 6, 7, X, X, X, X
0, 1, 2, 3, X, X, X, X 4, 5, 6, 7, X, X, X, X
1, 2, 4, 5
0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7
0 1, 2, 3, 0, 5, 6, 7, 4 1, 0, 3, 2, 5, 4, 7, 6
0 1 0 2, 3, 0, 1, 6, 7, 4, 5 2, 3, 0, 1, 6, 7, 4, 5

Read
0 1 3, 0, 1, 2, 7, 4, 5, 6 3, 2, 1, 0, 7, 6, 5, 4 1 0 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3
1 0 1 5, 6, 7, 4, 1, 2, 3, 0 5, 4, 7, 6, 1, 0, 3, 2
1 0 6, 7, 4, 5, 2, 3, 0, 1 6, 7, 4, 5, 2, 3, 0, 1
1 7, 4, 5, 6, 3, 0, 1, 2 7, 6, 5, 4, 3, 2, 1, 0

Write

V 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 2, 4

Note In case of burst length being fixed to 4 by MR0 setting, the internal write operation starts two clock cycles earlier than for the BL8 mode. This means that the starting point for tWR and tWTR will be pulled in by two clocks. In case of burst length being selected on-the-fly via A12/BC#, the internal write operation starts at the same point in time like a burst of 8 write operation. This means that during on-the-fly control, the starting point for tWR and tWTR will not be pulled in by two clocks.

Note 0~7 bit number is value of CA[2:0] that causes this bit to be the first read during a burst.

Note T Output driver for data and strobes are in high impedance. Note V a valid logic level 0 or 1 , but respective buffer input ignores level on input pins. Note X Don’t Care.
- DLL Reset

The DLL Reset bit is self-clearing, meaning it returns back to the value of ‘0’ after the DLL reset function has been
issued. Once the DLL is enabled, a subsequent DLL Reset should be applied. Anytime the DLL reset function is used, tDLLK must be met before any functions that require the DLL can be used i.e. Read commands or ODT synchronous operations.
- Write Recovery

The programmed WR value MR0 bits A9, A10, and A11 is used for the auto precharge feature along with tRP to determine tDAL. WR write recovery for auto-precharge min in clock cycles is calculated by dividing tWR ns by tCK ns and rounding up to the next integer WR min [cycles] = Roundup tWR [ns]/tCK [ns] . The WR must be programmed to be equal or larger than tWR min .
burst order is switched on nibble base A [2]=0b, Burst order 0,1,2,3 * A[2]=1b, Burst order 4,5,6,7 * A[9:3] don’t care A10/AP don’t care A12/BC Selects burst chop mode on-the-fly, if enabled within MR0. A11 if available don’t care Regular interface functionality during register reads Support two Burst Ordering which are switched with A2 and A[1:0]=00b. Support of read burst chop MRS and on-the-fly via A12/BC All other address bits remaining column address bits including A10, all bank address bits will be ignored by the

DDR3L SDRAM. Regular read latencies and AC timings apply. DLL must be locked prior to MPR Reads.

NOTE * Burst order bit 0 is assigned to LSB and burst order bit 7 is assigned to MSB of the selected MPR agent.

Table MPR MR3 Register Definition

MR3 A[2]

MR3 A[1:0]

Function

Burst Length

Read Predefined

Pattern for System

Calibration

Read Address A[2:0]

Burst Order and Data Pattern
000b

Burst order 0, 1, 2, 3, 4, 5, 6, 7

Pre-defined Data Pattern
[0, 1, 0, 1, 0, 1, 0, 1]
000b

Burst order 0, 1, 2, 3

Pre-defined Data Pattern
[0, 1, 0, 1]
100b

Burst order 4, 5, 6, 7

Pre-defined Data Pattern
[0, 1, 0, 1]
000b

Burst order 0, 1, 2, 3, 4, 5, 6, 7
000b

Burst order 0, 1, 2, 3
100b

Burst order 4, 5, 6, 7
000b

Burst order 0, 1, 2, 3, 4, 5, 6, 7
000b

Burst order 0, 1, 2, 3
100b

Burst order 4, 5, 6, 7
000b

Burst order 0, 1, 2, 3, 4, 5, 6, 7
000b

Burst order 0, 1, 2, 3

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Datasheet ID: AS4C32M16D3L-12BCN 516132