AS4C32M16D2-25BCNTR

AS4C32M16D2-25BCNTR Datasheet

AS4C32M16D2

Part	Datasheet
AS4C32M16D2-25BCNTR	AS4C32M16D2-25BCNTR (pdf)

Related Parts	Information
AS4C32M16D2-25BCN	AS4C32M16D2-25BCN
AS4C32M16D2-25BINTR	AS4C32M16D2-25BINTR
AS4C32M16D2-25BIN	AS4C32M16D2-25BIN

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AS4C32M16D2 Confidential 512M 32M x 16 bit DDRII Synchronous DRAM SDRAM • JEDEC Standard Compliant • JEDEC standard 1.8V I/O SSTL_18-compatible • Power supplies VDD & VDDQ = +1.8V  0.1V • Supports JEDEC clock jitter specification • Fully synchronous operation • Fast clock rate 400 MHz • Differential Clock, CK & CK# • Bidirectional single/differential data strobe -DQS & DQS# • 4 internal banks for concurrent operation • 4-bit prefetch architecture • Internal pipeline architecture • Precharge & active power down • Programmable Mode & Extended Mode registers • Posted CAS# additive latency AL 0, 1, 2, 3, 4, 5, 6 • WRITE latency = READ latency - 1 tCK • Burst lengths 4 or 8 • Burst type Sequential / Interleave • DLL enable/disable • Off-Chip Driver OCD -Impedance Adjustment -Adjustable data-output drive strength • On-die termination ODT • RoHS compliant • Auto Refresh and Self Refresh • Operating temperature range - Commercial -0 ~ 85°C - Industrial -40 ~ 95°C • 8192 refresh cycles / 64ms - Average refresh period 7.8µs 0℃ +85℃ 3.9µs +85℃ +95℃ • 84-ball 8x12.5x1.2mm max FBGA - Pb and Halogen Free Overview The AS4C32M16D2 DDR2 SDRAM is a high-speed CMOS Double-Data-Rate-Two DDR2 , synchronous dynamic random-access memory SDRAM containing 512 Mbits in a 16-bit wide data I/Os. It is internally configured as a quad bank DRAM, 4 banks x 8Mb addresses x 16 I/Os The device is designed to comply with DDR2 DRAM key features such as posted CAS# with additive latency, Write latency = Read latency -1, Off-Chip Driver OCD impedance adjustment, and On Die Termination ODT . All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks CK rising and CK# falling All I/Os are synchronized with a pair of bidirectional strobes DQS and DQS# in a source synchronous fashion. The address bus is used to convey row, column, and bank address information in RAS # , CAS# multiplexing style. Accesses begin with the registration of a Bank Activate command, and then it is followed by a Read or Write command. Read and write accesses to the DDR2 SDRAM are 4 or 8-bit burst oriented accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Operating the four memory banks in an interleaved fashion allows random access operation to occur at a higher rate than is possible with standard DRAMs. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. A sequential and gapless data rate is possible depending on burst length, CAS latency, and speed grade of the device. Ordering Information Clock Frequency Data Rate AS4C32M16D2-25BCN 400MHz 800Mbps/pin AS4C32M16D2-25BIN 400MHz 800Mbps/pin B indicates 84-ball x 1.2mm TFBGA package C indicates Commercial temp. I indicates Industrial temp. N indicates Pb and Halogen Free ROHS Package 84-ball FBGA 84-ball FBGA Temperature Commercial Industrial Temp Range -0° ~ 85°C -40° ~ 95°C Alliance Memory Inc. 551 Taylor Way, San Carlos, CA 94070 TEL 650 610-6800 FAX 650 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice. Feb. /2013 AS4C32M16D2 Figure Ball Assignment FBGA Top View A VDD B DQ14 VSSQ UDM C VDDQ DQ9 VDDQ D DQ12 VSSQ DQ11 E VDD VSSQ LDM G VDDQ DQ1 VDDQ VSSQ VDDL VREF N VSS R VDD VSSQ UDQS# VDDQ UDQS. VDDQ VSSQ DQ8 DQ15 VDDQ DQ10 VSSQ DQ13 VSSQ LDQS# VDDQ LDQS VSSQ DQ7 VDDQ DQ0 VDDQ Burst mode operation is used to provide a constant flow of data to memory locations Write cycle , or from memory locations Read cycle . The parameters that define how the burst mode will operate are burst sequence and burst length. The DDR2 SDRAM supports 4 bit and 8 bit burst modes only. For 8 bit burst mode, full interleave address ordering is supported, however, sequential address ordering is nibble based for ease of implementation. The burst length is programmable and defined by the addresses A0 ~ A2 of the MRS. The burst type, either sequential or interleaved, is programmable and defined by the address bit 3 A3 of the MRS. Seamless burst Read or Write operations are supported. Interruption of a burst Read or Write operation is prohibited, when burst length = 4 is programmed. For burst interruption of a Read or Write burst when burst length = 8 is used, see the “Burst Interruption“ section of this datasheet. A Burst Stop command is not supported on DDR2 SDRAM devices. Alliance Memory Inc. 551 Taylor Way, San Carlos, CA 94070 TEL 650 610-6800 FAX 650 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice. Feb. /2013 AS4C32M16D2 Table 12.Burst Definition, Addressing Sequence of Sequential and Interleave Mode Burst Length 4 Start Address A2 A1 A0 Sequential 0, 1, 2, 3 1, 2, 3, 0 2, 3, 0, 1 3, 0, 1, 2 0, 1, 2, 3, 4, 5, 6, 7 1, 2, 3, 0, 5, 6, 7, 4 2, 3, 0, 1, 6, 7, 4, 5 3, 0, 1, 2, 7, 4, 5, 6 4, 5, 6, 7, 0, 1, 2, 3 5, 6, 7, 4, 1, 2, 3, 0 6, 7, 4, 5, 2, 3, 0, 1 7, 4, 5, 6, 3, 0, 1, 2 Interleave 0, 1, 2, 3 1, 0, 3, 2, 3, 0, 1 3, 2, 1, 0, 1, 2, 3, 4, 5, 6, 7 1, 0, 3, 2, 5, 4, 7, 6 2, 3, 0, 1, 6, 7, 4, 5 3, 2, 1, 0, 7, 6, 5, 4, 5, 6, 7, 0, 1, 2, 3 5, 4, 7, 6, 1, 0, 3, 2 6, 7, 4, 5, 2, 3, 0, 1 7, 6, 5, 4, 3, 2, 1, 0 Burst read command The Burst Read command is initiated by having CS# and CAS# LOW while holding RAS# and WE# HIGH at the rising edge of the clock. The address inputs determine the starting column address for the burst. The delay from the start of the command to when the data from the first cell appears on the outputs is equal to the value of the Read Latency RL . The data strobe output DQS is driven LOW 1 clock cycle before valid data DQ is driven onto the data bus. The first bit of the burst is synchronized with the rising edge of the data strobe DQS . Each subsequent data-out appears on the DQ pin in phase with the DQS signal in a source synchronous manner. The RL is equal to an additive latency AL plus CAS Latency CL . The CL is defined by the Mode Register Set MRS , similar to the existing SDR and DDR SDRAMs. The AL is defined by the Extended Mode Register Set 1 EMRS DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the EMRS “Enable DQS” mode bit timing advantages of differential mode are realized in system design. The method by which the DDR2 SDRAM pin timings are measured is mode dependent. In single ended mode, timing relationships are measured relative to the rising or falling edges of DQS crossing at VREF. In differential mode, these timing relationships are measured relative to the crosspoint of DQS and its complement, DQS#. This distinction in timing methods is guaranteed by design and characterization. Note that when differential data strobe mode is disabled via the EMRS, the complementary pin, DQS#, must be tied externally to VSS through a 20 Ω to 10 KΩresistor to insure proper operation. Burst write operation The Burst Write command is initiated by having CS#, CAS# and WE# LOW while holding RAS# HIGH at the rising edge of the clock. The address inputs determine the starting column address. Write latency WL is defined by a Read latency RL minus one and is equal to AL + CL -1 ;and is the number of clocks of delay that are required from the time the Write command is registered to the clock edge associated to the first DQS strobe. A data strobe signal DQS should be driven LOW preamble one clock prior to the WL. The first data bit of the burst cycle must be applied to the DQ pins at the first rising edge of the DQS following the preamble. The tDQSS specification must be satisfied for each positive DQS transition to its associated clock edge during write cycles. The subsequent burst bit data are issued on successive edges of the DQS until the burst length is completed, which is 4 or 8 bit burst. When the burst has finished, any additional data supplied to the DQ pins will be ignored. The DQ Signal is ignored after the burst write operation is complete. The time from the completion of the burst Write to bank precharge is the write recovery time WR . DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the EMRS “Enable DQS” mode bit timing advantages of differential mode are realized in system design. The method by which the DDR2 SDRAM pin timings are measured is mode dependent. Alliance Memory Inc. 551 Taylor Way, San Carlos, CA 94070 TEL 650 610-6800 FAX 650 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice. Feb. /2013 AS4C32M16D2 In single ended mode, timing relationships are measured relative to the rising or falling edges of DQS crossing at the specified AC/DC levels. In differential mode, these timing relationships are measured relative to the crosspoint of DQS and its complement, DQS#. This distinction in timing methods is guaranteed by design and characterization. Note that when differential data strobe mode is disabled via the EMRS, the complementary pin, DQS#, must be tied externally to VSS through a 20Ω to 10KΩ resistor to insure proper operation. Alliance Memory Inc. 551 Taylor Way, San Carlos, CA 94070 TEL 650 610-6800 FAX 650 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice. Feb. /2013 AS4C32M16D2 Write data mask One Write data mask DM pin for each 8 data bits DQ will be supported on DDR2 SDRAMs, Consistent with the implementation on DDR SDRAMs. It has identical timings on Write operations as the data bits, and though used in a uni-directional manner, is internally loaded identically to data bits to insure matched system timing. DM is not used during read cycles. Precharge operation The Precharge command is used to precharge or close a bank that has been activated. The Precharge Command is triggered when CS#, RAS# and WE# are LOW and CAS# is HIGH at the rising edge of the clock. The Precharge Command can be used to precharge each bank independently or all banks simultaneously. Three address bits A10, BA1, and BA0 are used to define which bank to precharge when the command is issued. Table 13.Bank Selection for Precharge by address bits LOW HIGH LOW HIGH DON’T CARE LOW HIGH LOW HIGH DON’T CARE Precharged Bank s

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AS4C32M16D2

Confidential
512M 32M x 16 bit DDRII Synchronous DRAM SDRAM
• JEDEC Standard Compliant
• JEDEC standard 1.8V I/O SSTL_18-compatible
• Power supplies VDD & VDDQ = +1.8V  0.1V
• Supports JEDEC clock jitter specification
• Fully synchronous operation
• Fast clock rate 400 MHz
• Differential Clock, CK & CK#
• Bidirectional single/differential data strobe
-DQS & DQS#
• 4 internal banks for concurrent operation
• 4-bit prefetch architecture
• Internal pipeline architecture
• Precharge & active power down
• Programmable Mode & Extended Mode registers
• Posted CAS# additive latency AL 0, 1, 2, 3, 4, 5, 6
• WRITE latency = READ latency - 1 tCK
• Burst lengths 4 or 8
• Burst type Sequential / Interleave
• DLL enable/disable
• Off-Chip Driver OCD
-Impedance Adjustment -Adjustable data-output drive strength
• On-die termination ODT
• RoHS compliant
• Auto Refresh and Self Refresh
• Operating temperature range - Commercial -0 ~ 85°C - Industrial -40 ~ 95°C
• 8192 refresh cycles / 64ms - Average refresh period 7.8µs 0℃ +85℃ 3.9µs +85℃ +95℃
• 84-ball 8x12.5x1.2mm max FBGA - Pb and Halogen Free

Overview

The AS4C32M16D2 DDR2 SDRAM is a high-speed CMOS Double-Data-Rate-Two DDR2 , synchronous dynamic random-access memory SDRAM containing 512 Mbits in a 16-bit wide data I/Os. It is internally configured as a quad bank DRAM, 4 banks x 8Mb addresses x 16 I/Os

The device is designed to comply with DDR2 DRAM key features such as posted CAS# with additive latency, Write latency = Read latency -1, Off-Chip Driver OCD impedance adjustment, and On Die Termination ODT .

All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks CK rising and CK# falling All I/Os are synchronized with a pair of bidirectional strobes DQS and DQS# in a source synchronous fashion. The address bus is used to convey row, column, and bank address information in RAS # , CAS# multiplexing style. Accesses begin with the registration of a Bank Activate command, and then it is followed by a Read or Write command. Read and write accesses to the DDR2 SDRAM are 4 or 8-bit burst oriented accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Operating the four memory banks in an interleaved fashion allows random access operation to occur at a higher rate than is possible with standard DRAMs. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. A sequential and gapless data rate is possible depending on burst length, CAS latency, and speed grade of the device.
Ordering Information

Clock Frequency Data Rate

AS4C32M16D2-25BCN 400MHz
800Mbps/pin

AS4C32M16D2-25BIN 400MHz
800Mbps/pin

B indicates 84-ball x 1.2mm TFBGA package

C indicates Commercial temp.

I indicates Industrial temp.

N indicates Pb and Halogen Free ROHS

Package 84-ball FBGA 84-ball FBGA

Temperature Commercial Industrial

Temp Range -0° ~ 85°C -40° ~ 95°C

Alliance Memory Inc. 551 Taylor Way, San Carlos, CA 94070

TEL 650 610-6800

FAX 650 620-9211

Alliance Memory Inc. reserves the right to change products or specification without notice.

Feb. /2013

AS4C32M16D2

Figure Ball Assignment FBGA Top View

A VDD

B DQ14 VSSQ UDM

C VDDQ DQ9 VDDQ

D DQ12 VSSQ DQ11

E VDD

VSSQ LDM

G VDDQ DQ1 VDDQ

VSSQ

VDDL VREF

N VSS

R VDD

VSSQ

UDQS#

VDDQ

UDQS. VDDQ

VSSQ DQ8

DQ15 VDDQ

DQ10 VSSQ DQ13

VSSQ LDQS# VDDQ

LDQS VSSQ DQ7

VDDQ DQ0 VDDQ
Burst mode operation is used to provide a constant flow of data to memory locations Write cycle , or from memory locations Read cycle . The parameters that define how the burst mode will operate are burst sequence and burst length. The DDR2 SDRAM supports 4 bit and 8 bit burst modes only. For 8 bit burst mode, full interleave address ordering is supported, however, sequential address ordering is nibble based for ease of implementation. The burst length is programmable and defined by the addresses A0 ~ A2 of the MRS. The burst type, either sequential or interleaved, is programmable and defined by the address bit 3 A3 of the MRS. Seamless burst Read or Write operations are supported. Interruption of a burst Read or Write operation is prohibited, when burst length = 4 is programmed. For burst interruption of a Read or Write burst when burst length = 8 is used, see the “Burst Interruption“ section of this datasheet. A Burst Stop command is not supported on DDR2 SDRAM devices.

Alliance Memory Inc. 551 Taylor Way, San Carlos, CA 94070

TEL 650 610-6800

FAX 650 620-9211

Alliance Memory Inc. reserves the right to change products or specification without notice.

Feb. /2013

AS4C32M16D2

Table 12.Burst Definition, Addressing Sequence of Sequential and Interleave Mode

Burst Length 4

Start Address

A2 A1 A0

Sequential
0, 1, 2, 3 1, 2, 3, 0 2, 3, 0, 1 3, 0, 1, 2 0, 1, 2, 3, 4, 5, 6, 7 1, 2, 3, 0, 5, 6, 7, 4 2, 3, 0, 1, 6, 7, 4, 5 3, 0, 1, 2, 7, 4, 5, 6 4, 5, 6, 7, 0, 1, 2, 3 5, 6, 7, 4, 1, 2, 3, 0 6, 7, 4, 5, 2, 3, 0, 1 7, 4, 5, 6, 3, 0, 1, 2

Interleave
0, 1, 2, 3 1, 0, 3, 2, 3, 0, 1 3, 2, 1, 0, 1, 2, 3, 4, 5, 6, 7 1, 0, 3, 2, 5, 4, 7, 6 2, 3, 0, 1, 6, 7, 4, 5 3, 2, 1, 0, 7, 6, 5, 4, 5, 6, 7, 0, 1, 2, 3 5, 4, 7, 6, 1, 0, 3, 2 6, 7, 4, 5, 2, 3, 0, 1 7, 6, 5, 4, 3, 2, 1, 0

Burst read command

The Burst Read command is initiated by having CS# and CAS# LOW while holding RAS# and WE# HIGH at the rising edge of the clock. The address inputs determine the starting column address for the burst. The delay from the start of the command to when the data from the first cell appears on the outputs is equal to the value of the Read Latency RL . The data strobe output DQS is driven LOW 1 clock cycle before valid data DQ is driven onto the data bus. The first bit of the burst is synchronized with the rising edge of the data strobe DQS . Each subsequent data-out appears on the DQ pin in phase with the DQS signal in a source synchronous manner. The RL is equal to an additive latency AL plus CAS Latency CL . The CL is defined by the Mode Register Set MRS , similar to the existing SDR and DDR SDRAMs. The AL is defined by the Extended Mode Register Set 1 EMRS DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the EMRS “Enable DQS” mode bit timing advantages of differential mode are realized in system design. The method by which the DDR2 SDRAM pin timings are measured is mode dependent. In single ended mode, timing relationships are measured relative to the rising or falling edges of DQS crossing at VREF. In differential mode, these timing relationships are measured relative to the crosspoint of DQS and its complement, DQS#. This distinction in timing methods is guaranteed by design and characterization. Note that when differential data strobe mode is disabled via the EMRS, the complementary pin, DQS#, must be tied externally to VSS through a 20 Ω to 10 KΩresistor to insure proper operation.

Burst write operation

The Burst Write command is initiated by having CS#, CAS# and WE# LOW while holding RAS# HIGH at the rising edge of the clock. The address inputs determine the starting column address. Write latency WL is defined by a Read latency RL minus one and is equal to AL + CL -1 ;and is the number of clocks of delay that are required from the time the Write command is registered to the clock edge associated to the first DQS strobe. A data strobe signal DQS should be driven LOW preamble one clock prior to the WL. The first data bit of the burst cycle must be applied to the DQ pins at the first rising edge of the DQS following the preamble. The tDQSS specification must be satisfied for each positive DQS transition to its associated clock edge during write cycles. The subsequent burst bit data are issued on successive edges of the DQS until the burst length is completed, which is 4 or 8 bit burst. When the burst has finished, any additional data supplied to the DQ pins will be ignored. The DQ Signal is ignored after the burst write operation is complete. The time from the completion of the burst Write to bank precharge is the write recovery time WR . DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the EMRS “Enable DQS” mode bit timing advantages of differential mode are realized in system design. The method by which the DDR2 SDRAM pin timings are measured is mode dependent.

Alliance Memory Inc. 551 Taylor Way, San Carlos, CA 94070

TEL 650 610-6800

FAX 650 620-9211

Alliance Memory Inc. reserves the right to change products or specification without notice.

Feb. /2013

AS4C32M16D2

In single ended mode, timing relationships are measured relative to the rising or falling edges of DQS crossing at the specified AC/DC levels. In differential mode, these timing relationships are measured relative to the crosspoint of DQS and its complement, DQS#. This distinction in timing methods is guaranteed by design and characterization. Note that when differential data strobe mode is disabled via the EMRS, the complementary pin, DQS#, must be tied externally to VSS through a 20Ω to 10KΩ resistor to insure proper operation.

Alliance Memory Inc. 551 Taylor Way, San Carlos, CA 94070

TEL 650 610-6800

FAX 650 620-9211

Alliance Memory Inc. reserves the right to change products or specification without notice.

Feb. /2013

AS4C32M16D2

Write data mask

One Write data mask DM pin for each 8 data bits DQ will be supported on DDR2 SDRAMs, Consistent with the implementation on DDR SDRAMs. It has identical timings on Write operations as the data bits, and though used in a uni-directional manner, is internally loaded identically to data bits to insure matched system timing. DM is not used during read cycles.

Precharge operation

The Precharge command is used to precharge or close a bank that has been activated. The Precharge Command is triggered when CS#, RAS# and WE# are LOW and CAS# is HIGH at the rising edge of the clock. The Precharge Command can be used to precharge each bank independently or all banks simultaneously. Three address bits A10, BA1, and BA0 are used to define which bank to precharge when the command is issued.

Table 13.Bank Selection for Precharge by address bits

LOW HIGH

LOW HIGH DON’T CARE

LOW HIGH LOW HIGH DON’T CARE

Precharged Bank s

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Datasheet ID: AS4C32M16D2-25BCNTR 516131