AS4C2M32S-6TCN

AS4C2M32S-6TCN Datasheet

AS4C2M32S

Part	Datasheet
AS4C2M32S-6TCN	AS4C2M32S-6TCN (pdf)

Related Parts	Information
AS4C2M32S-7TCN	AS4C2M32S-7TCN
AS4C2M32S-5TCNTR	AS4C2M32S-5TCNTR
AS4C2M32S-7TCNTR	AS4C2M32S-7TCNTR
AS4C2M32S-6TIN	AS4C2M32S-6TIN
AS4C2M32S-6TINTR	AS4C2M32S-6TINTR
AS4C2M32S-5TCN	AS4C2M32S-5TCN
AS4C2M32S-6TCNTR	AS4C2M32S-6TCNTR

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AS4C2M32S Confidential 2M x 32 bit Synchronous DRAM SDRAM • Fast access time ns  • Fast Clock rate 200/166/143 MHz  • Fully synchronous operation  • Internal pipelined architecture  • Four internal banks 512K x 32bit x 4bank  • Programmable Mode  - CAS Latency 2 or 3 - Burst Length 1, 2, 4, 8, or full page - Burst Type Sequential or Interleaved - Burst-Read-Single-Write • Burst stop function  • Individual byte controlled by DQM0-3  • Auto Refresh and Self Refresh  • Operating temperature range  - Commercial 0 ~ 70°C - Industrial -40 ~ 85°C • 4096 refresh cycles/64ms  • Single +3.3V ± 0.3V power supply  • Interface LVTTL  • 86-pin 400 x 875 mil plastic TSOP II  package, 0.50mm pin pitch  - Pb and Halogen Free Overview The 64Mb SDRAM is a high-speed CMOS synchronous DRAM containing 64 Mbits. It is internally configured as a quad 512K x 32 DRAM with a synchronous interface all signals are registered on the positive edge of the clock signal, CLK . Each of the 512K x 32 bit banks is organized as 2048 rows by 256 columns by 32 bits. Read and write accesses to the SDRAM are burst oriented accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command. The SDRAM provides for programmable Read or Write burst lengths of 1, 2, 4, 8, or full page, with a burst termination option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy to use. By having a programmable mode register, the system can choose the most suitable modes to maximize its performance. These devices are well suited for applications requiring high memory bandwidth. Table Key Specifications AS4C2M32S tCK3 Clock Cycle time min. tAC3 Access time from CLK max. tRAS Row Active time min. tRC Row Cycle time min. Table 2.Ordering Information Frequency AS4C2M32S-6TIN 166MHz AS4C2M32S-6TCN 166MHz AS4C2M32S-7TCN 143MHz AS4C2M32S-5TCN 200MHz T indicates TSOP II package N indicates Pb and Halogen Free -5/6/7 5/6/ ns 42/49 ns 60/70 ns Package 86-pin TSOP II 86-pin TSOP II 86-pin TSOP II 86-pin TSOPII Temperature Industrial Commercial Temp Range -40 ~ 85°C 0 ~ 70°C 0 ~ 70°C 0 ~ 70°C Confidential May. /2014 Figure Pin Assignment Top View VDD 1 DQ0 2 VDDQ 3 DQ1 4 DQ2 5 VSSQ 6 DQ3 7 DQ4 8 VDDQ 9 DQ5 10 DQ6 11 VSSQ 12 DQ7 13 NC 14 VDD 15 DQM0 16 WE# 17 CAS# 18 RAS# 19 CS# 20 NC 21 BA0 22 BA1 23 A10/AP 24 A0 25 A1 26 A2 27 DQM2 28 VDD 29 NC 30 DQ16 31 VSSQ 32 DQ17 33 DQ18 34 VDDQ 35 DQ19 36 DQ20 37 VSSQ 38 DQ21 39 DQ22 40 VDDQ 41 DQ23 42 VDD 43 DQ15 84 VSSQ 83 DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 VDDQ DQM1 DQM3 DQ31 VDDQ DQ30 DQ29 VSSQ DQ28 DQ27 VDDQ DQ26

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AS4C2M32S

Confidential
2M x 32 bit Synchronous DRAM SDRAM
• Fast access time ns 
• Fast Clock rate 200/166/143 MHz 
• Fully synchronous operation 
• Internal pipelined architecture 
• Four internal banks 512K x 32bit x 4bank 
• Programmable Mode 
- CAS Latency 2 or 3
- Burst Length 1, 2, 4, 8, or full page
- Burst Type Sequential or Interleaved
- Burst-Read-Single-Write
• Burst stop function 
• Individual byte controlled by DQM0-3 
• Auto Refresh and Self Refresh 
• Operating temperature range 
- Commercial 0 ~ 70°C
- Industrial -40 ~ 85°C
• 4096 refresh cycles/64ms 
• Single +3.3V ± 0.3V power supply 
• Interface LVTTL 
• 86-pin 400 x 875 mil plastic TSOP II  package, 0.50mm pin pitch 
- Pb and Halogen Free

Overview

The 64Mb SDRAM is a high-speed CMOS synchronous DRAM containing 64 Mbits. It is internally configured as a quad 512K x 32 DRAM with a synchronous interface all signals are registered on the positive edge of the clock signal, CLK . Each of the 512K x 32 bit banks is organized as 2048 rows by 256 columns by 32 bits. Read and write accesses to the SDRAM are burst oriented accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command.

The SDRAM provides for programmable Read or Write burst lengths of 1, 2, 4, 8, or full page, with a burst termination option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy to use.

By having a programmable mode register, the system can choose the most suitable modes to maximize its performance. These devices are well suited for applications requiring high memory bandwidth.

Table Key Specifications AS4C2M32S
tCK3 Clock Cycle time min. tAC3 Access time from CLK max. tRAS Row Active time min. tRC Row Cycle time min.
Table 2.Ordering Information

Frequency

AS4C2M32S-6TIN 166MHz

AS4C2M32S-6TCN 166MHz

AS4C2M32S-7TCN 143MHz

AS4C2M32S-5TCN 200MHz

T indicates TSOP II package N indicates Pb and Halogen Free
-5/6/7 5/6/ ns
42/49 ns
60/70 ns

Package 86-pin TSOP II 86-pin TSOP II 86-pin TSOP II 86-pin TSOPII

Temperature Industrial Commercial

Temp Range -40 ~ 85°C 0 ~ 70°C 0 ~ 70°C 0 ~ 70°C

Confidential

May. /2014

Figure Pin Assignment Top View

VDD 1 DQ0 2 VDDQ 3 DQ1 4 DQ2 5 VSSQ 6 DQ3 7 DQ4 8 VDDQ 9 DQ5 10 DQ6 11 VSSQ 12 DQ7 13

NC 14 VDD 15 DQM0 16 WE# 17 CAS# 18 RAS# 19 CS# 20

NC 21 BA0 22 BA1 23 A10/AP 24

A0 25 A1 26 A2 27 DQM2 28 VDD 29 NC 30 DQ16 31 VSSQ 32 DQ17 33 DQ18 34 VDDQ 35 DQ19 36 DQ20 37 VSSQ 38 DQ21 39 DQ22 40 VDDQ 41 DQ23 42 VDD 43

DQ15
84 VSSQ
83 DQ14

DQ13

VDDQ

DQ12

DQ11

VSSQ

DQ10

VDDQ

DQM1

DQM3

DQ31

VDDQ

DQ30

DQ29

VSSQ

DQ28

DQ27

VDDQ

DQ26

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Datasheet ID: AS4C2M32S-6TCN 516129