A8904
Part | Datasheet |
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A8904SLP (pdf) |
Related Parts | Information |
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A8904SLP-T |
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A8904SLPTR-T |
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A8904SLB-T |
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A8904SLBTR |
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A8904SLBTR-T |
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A8904SLPTR |
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A8904SLB |
PDF Datasheet Preview |
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A8904 3-Phase Brushless DC Motor Controller/Driver with Back EMF Sensing Pin-for-pin replacement for A8902CLBA Start-up commutation circuitry Sensorless commutation circuitry Option of external sector data tachometer signal Option of external speed control Oscillator operation up to 20 MHz Programmable overcurrent limit Transconductance gain options 500 mA/V or 250 mA/V Programmable watchdog timer Directional control Serial port interface TTL-compatible inputs System diagnostics data-out ported in real time Dynamic braking through serial port or external terminal Packages: Not to scale 28-pin TSSOP with exposed thermal pad Package LP 24-pin SOICW with internally fused pins LB package The A8904 is a 3-phase brushless DC motor controller/driver designed for applications where accurate control of high-speed motors is required. The three half-bridge outputs are low on-resistance, N-channel DMOS devices capable of driving up to 1.2A. TheA8904 provides complete, reliable, self-contained back EMF sensing, motor start-up, and running algorithms. A programmable digital frequency-locked loop speed control circuit together with the linear current control circuitry provides precise motor speed regulation. A serial port allows the user to program various features and modes of operation, such as the speed control parameters, start-up current limit, sleep mode, direction, and diagnostic modes. The A8904 is fabricated in the BCD Bipolar CMOS DMOS process, an advanced mixed-signal technology that combines bipolar, analog, and digital CMOS, with DMOS power devices. The device is provided in a 24-pin wide-body SOIC package, with 4 internally-fused leads for enhanced thermal dissipation package LB , and a thin mm overall height , 28-pin TSSOP package with an exposed thermal pad Package LP . Both packages are lead Pb free, with 100% matte tin leadframe plating. Functional Block Diagram LOGIC SUPPLY C D2 C ST BRAKE C RES OUT A OUT B CENTERTAP OUTC COMMUTATION LOGIC SEQUENCE LOGIC BRAKE FCOM COMMUTATION DELAY START-UP OSC. BLANK BOOST CHARGE PUMP C WD SECTOR DATA FREQUENCYLOCKED LOOP WATCHDOG TIMER CHARGE PUMP CURRENT CONTROL RS DATA IN SERIAL PORT LOAD SUPPLY OUT A OUT B OUTC GROUND 26301.5H CHIP CLOCK RESET DATA OUT SELECT |
More datasheets: MA1RAE1200 | MA1RAE1700 | MA1RAP1700 | SC000013 | MA3CG-S4 | A8904SLP-T | A8904SLPTR-T | A8904SLB-T | A8904SLBTR | A8904SLBTR-T |
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