AK9813BF

AK9813BF Datasheet

[AK9813B]

Part	Datasheet
AK9813BF	AK9813BF (pdf)

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ASAHI KASEI [AK9813B] AK9813B 12ch 8bit D/A Converter with EEPROM The AK9813B includes 12 channel, 8bit D/A converters with on-chip output buffer amps and it is capable to store the input digital data of each DAC by on-chip non-volatile CMOS EEPROM. The AK9813B is optimally designed for various circuit adjustments for consumer and industrial equipments and it is ideally suited for replacing mechanical trimmers. EEPROM SECTION words x 8bit x 4 organization for DAC D/A CONVERTER SECTION channels 8bit -1 to +2 LSB Output Voltage Range GND to VCC Operating Voltage Range section 2.7V to 5.5V section 4.5V to 5.5V, 2.7V to 3.6V 24pin VSOP SEL ECL CS/LD EA0 EA1 CLK DI Shift Register Control Logic Channel & Address 8 Decoder EEPROM 384bit 12 x 8bit x 4 VDD VSS 8bit Latch 8 8bit D/A 8bit Latch 8 8bit D/A 8bit Latch 8 8bit D/A AO11 8bit Latch 8 8bit D/A AO12 Block Diagram DAD04E-01 2002/11 ASAHI KASEI - Ordering Guide Model AK9813BF - Pin Layout AO1 AO2 AO3 AO4 AO5 AO6 AO7 AO8 AO9 AO10 AO11 AO12 Temp. Range -40 to +85°C AK9813BF 24pin VSOP VSS GND EA1 EA0 DI CLK CS/LD DO ECL SEL VCC VDD [AK9813B] Package 24-pin VSOP DAD04E-01 2002/11 ASAHI KASEI [AK9813B] - Pin Description 1 No. Pin Name 20 DI 17 DO 19 CLK 18 CS/LD Function I Serial Data Input Pin SEL=High 16bit data input format SEL=Low 14bit data input format O SEL=High CS I/F AK9813B reads out the data with LSB first in the 16bit shift register to DO pin synchronously with falling edge of CLK. When the CS pin is high level, the DO pin becomes high impedance. In STATUS mode, the DO pin outputs Ready/Busy status. SEL=Low LD I/F AK9813B reads out the data with MSB first in the 14bit shift register to DO pin synchronously with falling edge of CLK. In WRITE mode, the DO pin outputs Ready/Busy status. I Shift Clock Input Pin Schmitt-trigger input AK9813B takes in the data from DI pin synchronously with rising edge of the CLK pin. The data are transferred to the internal shift register. I Chip Select Input Pin Schmitt-trigger input The CS/LD is internally pulled up to VCC. SEL=High CS I/F After the CS pin changes from high level to low level while the CLK pin is high level, the AK9813B can input the data to the internal shift register and takes in the data from the DI pin synchronously with the rising edge of the CLK pin. After the CS pin changes from high level to low level while the CLK pin is low level, the AK9813B becomes the status mode and reads out the Ready/Busy status to the DO pin. When the CS pin changes from low level to high level regardless of Low/High level of the CLK pin, the AK9813B removes from the status mode to the normal mode. The CS pin usually should be kept at high level. SEL=Low LD I/F When the LD pin receives high pulse, the data of the internal shift register is transferred to the internal decoder or the register for D/A. The LD pin usually should be kept at low level. DAD04E-01 2002/11 ASAHI KASEI [AK9813B] - Pin Description 2 No. Pin Name 1 AO1 12 AO12 14 VCC 23 GND 13 VDD 24 VSS 21 EA0 22 EA1 16 ECL 15 SEL Function 8bit D/A outputs with OP-AMP Digital section Power Supply Pin Digital section Ground Pin OP-AMP and D/A section Power Supply OP-AMP and D/A section Ground I SEL=High CS I/F In AUTO READ operation and ECL operation, the address of EEPROM is selected by the EA0 and the EA1 pins. SEL=Low LD I/F The address of EEPROM is selected by the EA0 and the EA1 pins. I When the ECL pin receives high pulse, the data in EEPROM is automatically loaded to each corresponding D/A, starting from AO1 to AO12 in order. Then each D/A output is settled to pre-determined value. I Input Data Format Select Pin SEL=High CS I/F SEL=Low LD I/F After power-up, this pin should be kept either at "high" or "Low." DAD04E-01 2002/11 ASAHI KASEI

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ASAHI KASEI
[AK9813B]

AK9813B
12ch 8bit D/A Converter with EEPROM

The AK9813B includes 12 channel, 8bit D/A converters with on-chip output buffer amps and it is capable to store the input digital data of each DAC by on-chip non-volatile CMOS EEPROM. The AK9813B is optimally designed for various circuit adjustments for consumer and industrial equipments and it is ideally suited for replacing mechanical trimmers.

EEPROM SECTION words x 8bit x 4 organization for DAC

D/A CONVERTER SECTION
channels
8bit
-1 to +2 LSB

Output Voltage Range GND to VCC

Operating Voltage Range section 2.7V to 5.5V section 4.5V to 5.5V, 2.7V to 3.6V
24pin VSOP

SEL ECL CS/LD EA0 EA1

CLK DI

Shift Register

Control Logic Channel & Address 8 Decoder

EEPROM
384bit 12 x 8bit x 4

VDD VSS
8bit Latch 8 8bit D/A
8bit Latch 8 8bit D/A
8bit Latch 8 8bit D/A

AO11
8bit Latch 8 8bit D/A

AO12

Block Diagram

DAD04E-01
2002/11

ASAHI KASEI
- Ordering Guide

Model AK9813BF
- Pin Layout

AO1 AO2 AO3 AO4 AO5 AO6 AO7 AO8 AO9 AO10 AO11 AO12

Temp. Range -40 to +85°C

AK9813BF
24pin VSOP

VSS GND EA1 EA0 DI CLK CS/LD DO ECL SEL VCC VDD
[AK9813B]

Package 24-pin VSOP

DAD04E-01
2002/11

ASAHI KASEI
[AK9813B]
- Pin Description 1 No. Pin Name 20 DI 17 DO
19 CLK 18 CS/LD

Function

I Serial Data Input Pin SEL=High 16bit data input format

SEL=Low 14bit data input format

O SEL=High CS I/F AK9813B reads out the data with LSB first in the 16bit shift register to DO pin synchronously with falling edge of CLK. When the CS pin is high level, the DO pin becomes high impedance. In STATUS mode, the DO pin outputs Ready/Busy status.

SEL=Low LD I/F AK9813B reads out the data with MSB first in the 14bit shift register to DO pin synchronously with falling edge of CLK. In WRITE mode, the DO pin outputs Ready/Busy status.

I Shift Clock Input Pin Schmitt-trigger input AK9813B takes in the data from DI pin synchronously with rising edge of the CLK pin. The data are transferred to the internal shift register.

I Chip Select Input Pin Schmitt-trigger input The CS/LD is internally pulled up to VCC. SEL=High CS I/F After the CS pin changes from high level to low level while the CLK pin is high level, the AK9813B can input the data to the internal shift register and takes in the data from the DI pin synchronously with the rising edge of the CLK pin. After the CS pin changes from high level to low level while the CLK pin is low level, the AK9813B becomes the status mode and reads out the Ready/Busy status to the DO pin. When the CS pin changes from low level to high level regardless of Low/High level of the CLK pin, the AK9813B removes from the status mode to the normal mode. The CS pin usually should be kept at high level.

SEL=Low LD I/F When the LD pin receives high pulse, the data of the internal shift register is transferred to the internal decoder or the register for D/A. The LD pin usually should be kept at low level.

DAD04E-01
2002/11

ASAHI KASEI
[AK9813B]
- Pin Description 2 No. Pin Name 1 AO1 12 AO12 14 VCC 23 GND 13 VDD 24 VSS 21 EA0 22 EA1
16 ECL
15 SEL

Function
8bit D/A outputs with OP-AMP

Digital section Power Supply Pin Digital section Ground Pin OP-AMP and D/A section Power Supply OP-AMP and D/A section Ground I SEL=High CS I/F

In AUTO READ operation and ECL operation, the address of EEPROM is selected by the EA0 and the EA1 pins.

SEL=Low LD I/F The address of EEPROM is selected by the EA0 and the EA1 pins.

I When the ECL pin receives high pulse, the data in EEPROM is automatically loaded to each corresponding D/A, starting from AO1 to AO12 in order. Then each D/A output is settled to pre-determined value.

I Input Data Format Select Pin SEL=High CS I/F SEL=Low LD I/F After power-up, this pin should be kept either at "high" or "Low."

DAD04E-01
2002/11

ASAHI KASEI

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Datasheet ID: AK9813BF 515938