[AK4345]
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AK4345ET (pdf) |
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[AK4345] AK4345 100dB 96kHz 24-Bit Stereo 3.3V DAC with DIT GENERAL DESCRIPTION The AK4345 is a 24bit low voltage and low power stereo DAC with an integrated Digital Audio Interface Transmitter. The AK4345 uses an Advanced Multi-Bit architecture, which achieves 100dB dynamic range at 3.3V operation. The AK4345 integrates both switched-capacitor and continuous time filters, enabling performance for systems that have excessive clock jitter. The output voltage level can be set as high as 1Vrms. The AK4345 is offered in a space saving 16pin TSSOP package. FEATURES Sampling Rate 8kHz ~ 96kHz 24-Bit 8 times FIR Digital Filter SCF with high tolerance to clock jitter Single-ended output buffer Digital de-emphasis for 32kHz, 44.1kHz, 48kHz sampling I/F Format 24-Bit MSB justified, 16/24-Bit LSB justified, I2S Compatible Master Clock: 512/768/1024/1536fs for Half Speed 8kHz ~ 24kHz 256/384/512/768fs for Normal Speed 8kHz ~ 48kHz 128/192/256/384fs for Double Speed 48kHz ~ 96kHz µP Interface 4-wire/3-wire DIT Bypass mode CMOS Input Level THD+N -90dB DR, S/N 100dB DAC output voltage level 1Vrms DIT - AES3, IEC60958, S/PDIF, EIAJ CP1201 Compatible - 1-channel Transmission output - 42-bit Channel Status Buffer Power Supply to 3.6V Ta = −20 ~ 85°C 16pin TSSOP MS0635-E-01 -1- 2010/09 [AK4345] CSN CCLK CDTI CDTO SDTI1 LRCK BICK µP Interface MCLK De-emphasis Control Clock Divider Audio Data Interface 8X Interpolator 8X Interpolator Modulator Modulator SCF LPF SCF LPF TEST Figure AK4345 Block Diagram Mode= “0” CSN CCLK CDTI SDTI2 SDTI1 LRCK BICK µP Interface MCLK De-emphasis Control Clock Divider Audio Data Interface 8X Interpolator 8X Interpolator Modulator Modulator SCF LPF SCF LPF TEST Figure AK4345 Block Diagram Mode= “1” VDD VSS VCOM • Ordering Guide AK4345ET AKD4345 • Pin Layout MCLK BICK SDTI1 LRCK PDN CSN CCLK CDTI −20 ~ +85°C 16pin TSSOP 0.65mm pitch Evaluation Board for AK4345 CDTO/ SDTI2 AK4345 View VCOM LOUT ROUT TEST1 [AK4345] MS0635-E-01 -3- 2010/09 [AK4345] No. Pin Name 1 MCLK 2 BICK 3 SDTI1 4 LRCK 5 PDN 6 CSN 7 CCLK 8 CDTI 9 TEST1 10 ROUT 11 LOUT 12 VCOM 13 VSS 14 VDD CDTO SDTI2 16 TX PIN/FUNCTION I/O Function I Master Clock Input Pin I Audio Serial Data Clock Pin I Audio Serial Data Input Pin1 I Input Channel Clock Pin Full Power Down Mode Pin “L” Power down, “H” Power up I Chip Select Pin I Control Data Clock Pin I Control Data Input Pin TEST Pin This pin must be OPEN. |
More datasheets: 3852A-282-104A | 3852A-162-102A | 3852A-282-102A | 3852A-282-103A | 3852C-282-103A | 3852A-282-502A | EWM-W139F01E | CPC5604A | CPC5604ATR | SMP2-SOC |
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