AQD-D3L16R16-SM
AQD-D3L16R16-SM Datasheet
240Pin DDR3L 1600 RDIMM 16GB Based on 1Gx4 AQD-D3L16R16-SM
| Part | Datasheet |
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AQD-D3L16R16-SM |
AQD-D3L16R16-SM (pdf) |
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| 240Pin DDR3L 1600 RDIMM 16GB Based on 1Gx4 AQD-D3L16R16-SM Advantech AQD-D3L16R16-SM Datasheet Transcend Information Inc. 240Pin DDR3L 1600 RDIMM 16GB Based on 1Gx4 AQD-D3L16R16-SM DDR3L Registered DIMM is high-speed, low power memory module that use 1024Mx4bits DDR3L SDRAM in FBGA package, 1 pcs register in TFBGA package and a 2048 bits serial EEPROM on a 240-pin printed circuit board. DDR3L Registered DIMM is a Dual In-Line Memory Module and is intended for mounting into 240-pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges of DQS. Range of operation frequencies, programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. • RoHS compliant products. • JEDEC standard 1.35V 1.28V~1.45V Power supply • JEDEC standard 1.5V 1.425V~1.575V Power supply • VDDQ=1.35V 1.28V~1.45V & 1.5V 1.425V~1.575V • Clock Freq 800MHZ for 1600Mb/s/Pin • Programmable CAS Latency 11 • Programmable Additive Latency Posted /CAS : 0,CL-2 or CL-1 clock • Programmable /CAS Write Latency CWL = 8 DDR3-1600 • 8 bit pre-fetch • Burst Length 4, 8 • Bi-directional Differential Data-Strobe • Internal calibration through ZQ pin • On Die Termination with ODT pin • Serial presence detect with EEPROM • On DIMM thermal Sensor Pin Identification Function A0~A15, BA0~BA2 Address Inputs /RAS Row Address Strobe /CAS Column Address Strobe Write Enable /S0, /S1 Chip Selects CKE0, CKE1 Clock Enables ODT0, ODT1 On-die termination control DQ0~DQ63 Data Input/Output CB0~CB7 ECC Check bits DQS0~DQS8 /DQS0~/DQS8 Data Strobe DM0~DM8 Data Masks CK0, /CK0 Clocks Input /RESET Reset Pin /EVENT Temperature Event Pin /ERROUT Parity error found on address and control bus Par-In Parity bit for address and Control bus Core and I/O Power |
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