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RM24EP128A-BSNC-T (pdf) |
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RM24EP32 | RM24EP64 | RM24EP128 32/64/128-Kbit 2.7V Minimum Sterilization-Tolerant Boot Memory I2C Bus Preliminary Datasheet Gamma Radiation Tolerance 50 kGy e-Beam Sterilization Tolerance 50 kGy Memory array 32-Kbit, 64-Kbit, and 128-Kbit EEPROM-compatible boot memory Single supply voltage 2.7V - 3.6V 2-wire I2C interface Compatible with I2C bus modes: -100kHz -400kHz -1MHz Page size 32 byte / 64 byte -Byte and Page Write from 1 to 32 or 64 bytes -Byte Write within 50µs -Page Write within 1ms Random and sequential Read modes Write protect of the whole memory array RoHS-compliant and halogen-free packaging Based on Adesto's proprietary technology The RM24EP I2C EEPROM-compatible family of gamma-tolerant boot memory is comprised of devices with densities of 32 Kbit, 64 Kbit and 128 Kbit utilizing Adesto's CBRAM resistive memory technology. The memory devices use a single low-voltage supply ranging from 2.7V to 3.6V. The I2C device is accessed through a 2-wire I2C compatible interface consisting of a Serial Data SDA and Serial Clock SCL . The maximum clock SCL frequency is 1MHz. The devices have both byte write and page write capability. Page write is up to 32/64 bytes. Both random and sequential reads are available. Sequential reads are capable of reading the entire memory in one operation. External address pins permit up to eight devices on the same data bus. The devices are available in standard 8-pin SOIC packages. Block Diagram Figure Block Diagram RM24EP Pin/Signal Descriptions Table Pin/Signal Descriptions Symbol Pin # Name/Function LSB - Least Significant Bit, External Enable 2 External Enable E2 GND MSB - Most Significant Bit, External Enable 4 Ground 5 Serial Data 6 Serial Clock 7 Write Protect 8 Power Pin Out Diagram LSB of the three external enable bits E0, E1 and E2 . The levels of the external enable bits are compared with three enable bits in the received control byte to provide device selection. The device is selected if the comparison is true. Up to eight devices may be connected to the same bus by using different E0, E1, E2 combinations. The middle of the three external enable bits E0, E1 and E2 . The levels of the enable bits are compared with three enable bits in the received control byte to provide device selection. Also see the E0, E2 pin. MSB of the three external enable bits E0, E1 and E2 . The levels of the enable bits are compared with three enable bits in the received control byte to provide device selection. Also see the E0, E1 pin. Bidirectional pin used to transfer addresses and data into and data out of the device. It is an open-drain terminal, and therefore requires a pull-up resistor to VCC. Typical pull-up resistors are for 100KHz, and for 400KHz and 1MHz. For normal data transfer, SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the START and STOP conditions. This input is used to synchronize the data transfer from and to the device. SCL is an input only, since it is a slave-only device. Connect to either VCC or GND. If pulled low, write operations are enabled. If pulled high, write operations are inhibited, but read operations are not affected. Power supply pin RM24EP I2C Bus Protocol I2C is a 2-wire serial bus architecture with a clock pin SCL for synchronization, and a data pin SDA for data transfer. On the device the SDA pin is bi-directional. The SCL pin is an input only, because the device is slave-only. The SCL and SDA pins are both externally connected to a positive supply voltage via a current source or pull-up resistor. When the bus is free, both lines are high. The output stages of devices connected to the bus must have an open drain or open collector to perform a wired-AND function. Data on the I2C bus can be transferred at rates of up to 1 Mbit/s. The number of interfaces that may be connected to the bus is solely dependent on the bus capacitance limit of 400pF. The data on the SDA line must be stable during the high period of the clock. The high or low state of the data line can only change when the clock signal on the SCL line is low see Figure Ordering Information Ordering Detail RM24EP128A-BSNC-T Device Type RM24EP = I2C serial access bus Density 128 = 128 Kbit 64 = 64 Kbit 32 = 32 Kbit Voltage B = 2.7V to 3.6V Shipping Carrier B = Tube T = Tape & Reel Grade & Temperature Range C = Green, Commercial temperature 0-70°C Package SN = 8 lead SOIC , Narrow Ordering Codes Ordering Code RM24EP32B-BSNC-B RM24EP32B-BSNC-T RM24EP64B-BSNC-B RM24EP64B-BSNC-T RM24EP128A-BSNC-B RM24EP128A-BSNC-T Package Density 32 Kbit 64 Kbit 128 Kbit Operating Voltage 2.7V to 3.6V 2.7V to 3.6V 2.7V to 3.6V Device Grade Commercial 0C to 70C Commercial 0C to 70C Commercial 0C to 70C Ship Carrier Tube Reel Tube Reel Tube Reel Qty. Carrier 100 4000 100 4000 100 4000 Package Type 8-lead wide, Plastic Gull Wing Small Outline JEDEC SOIC RM24EP Date 4/2014 4/2014 6/2014 Comments Initial document release. Changed test condition in Icc1, Icc2 and Icc3 to Vcc=3.3. Removed references to 24C128A. Added Section 12 “Sterilization Tolerance” table. Updated AC and DC characterization specifications. RM24EP Corporate Office California | USA Adesto Headquarters 1250 Borregas Avenue Sunnyvale, CA 94089 Phone +1 Email: the Adesto logo, and are registered trademarks or trademarks of Adesto Technologies. All other marks are the property of their respective owners. Disclaimer Adesto Technologies Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Adesto's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Adesto are granted by the Company in connection with the sale of Adesto products, expressly or by implication. Adesto's products are not authorized for use as critical components in life support devices or systems. For Release Only Under Non-Disclosure Agreement NDA |
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