AT26DF161A-SU

AT26DF161A-SU Datasheet

AT26DF161A

Part	Datasheet
AT26DF161A-SU	AT26DF161A-SU (pdf)

Related Parts	Information
AT26DF161A-SSU	AT26DF161A-SSU
AT26DF321-SU	AT26DF321-SU
AT26DF161A-MU	AT26DF161A-MU

PDF Datasheet Preview
• Single 2.7V - 3.6V Supply • Serial Peripheral Interface SPI Compatible Supports SPI Modes 0 and 3 • 70 MHz Maximum Clock Frequency • Flexible, Uniform Erase Architecture 4-Kbyte Blocks 32-Kbyte Blocks 64-Kbyte Blocks Full Chip Erase • Individual Sector Protection with Global Protect/Unprotect Feature Thirty-two 64-Kbyte Physical Sectors • Hardware Controlled Locking of Protected Sectors • Flexible Programming Options Byte/Page Program 1 to 256 Bytes Sequential Program Mode Capability • Automatic Checking and Reporting of Erase/Program Failures • JEDEC Standard Manufacturer and Device ID Read Methodology • Low Power Dissipation 5 mA Active Read Current Typical 10 µA Deep Power-down Current Typical • Endurance 100,000 Program/Erase Cycles • Data Retention 20 Years • Complies with Full Industrial Temperature Range • Industry Standard Green Pb/Halide-free/RoHS Compliant Package Options 8-lead SOIC 150-mil and 208-mil wide 8-pad MLF 6 x 5 x mm 16-megabit 2.7-volt Only Serial Firmware Memory AT26DF161A For New Designs Use AT25DF161 The AT26DF161A is a serial interface Flash memory device designed for use in a wide variety of high-volume consumer-based applications in which program code is shadowed from Flash memory into embedded or external RAM for execution. The flexible erase architecture of the AT26DF161A, with its erase granularity as small as 4 Kbytes, makes it ideal for data storage as well, eliminating the need for additional data storage EEPROM devices. The physical sectoring and the erase block sizes of the AT26DF161A have been optimized to meet the needs of today’s code and data storage applications. By optimizing the size of the physical sectors and erase blocks, the memory space can be used much more efficiently. Because certain code modules and data storage segments must reside by themselves in their own protected sectors, the wasted and unused memory space that occurs with large sectored and large block erase Flash memory devices can be greatly reduced. This increased memory space efficiency allows additional code routines and data storage segments to be added while still maintaining the same overall device density. The AT26DF161A also offers a sophisticated method for protecting individual sectors against erroneous or malicious program and erase operations. By providing the ability to individually protect and unprotect sectors, a system can unprotect a specific sector to modify its contents while keeping the remaining sectors of the memory array securely protected. This is useful in applications where program code is patched or updated on a subroutine or module basis, or in applications where data storage segments need to be modified without running the risk of errant modifications to the program code segments. In addition to individual sector protection capabilities, the AT26DF161A incorporates Global Protect and Global Unprotect features that allow the entire memory array to be either protected or unprotected all at once. This reduces overhead during the manufacturing process since sectors do not have to be unprotected one-by-one prior to initial programming. Specifically designed for use in 3-volt systems, the AT26DF161A supports read, program, and erase operations with a supply voltage range of 2.7V to 3.6V. No separate voltage is required for programming and erasing. 2 AT26DF161A AT26DF161A Pin Descriptions and Pinouts Table Pin Descriptions Symbol CS SCK SI SO WP HOLD VCC GND Name and Function CHIP SELECT Asserting the CS pin selects the device. When the CS pin is deasserted, the device will be deselected and normally be placed in standby mode not Deep Power-down mode , and the SO pin will be in a high-impedance state. When the device is deselected, data will not be accepted on the SI pin. A high-to-low transition on the CS pin is required to start an operation, and a low-to-high transition is required to end an operation. When ending an internally self-timed operation such as a program or erase cycle, the device will not enter the standby mode until the completion of the operation. SERIAL CLOCK This pin is used to provide a clock to the device and is used to control the flow of data to and from the device. Command, address, and input data present on the SI pin is always latched on the rising edge of SCK, while output data on the SO pin is always clocked out on the falling edge of SCK. SERIAL INPUT The SI pin is used to shift data into the device. The SI pin is used for all data input including command and address sequences. Data on the SI pin is always latched on the rising edge of SCK. SERIAL OUTPUT The SO pin is used to shift data out from the device. Data on the SO pin is always clocked out on the falling edge of SCK. WRITE PROTECT The WP pin controls the hardware locking feature of the device. Please refer to section “Protection Commands and Features” on page 15 for more details on protection features and the WP pin. The WP pin is internally pulled-high and may be left floating if hardware-controlled protection will not be used. However, it is recommended that the WP pin also be externally connected to VCC whenever possible. HOLD The HOLD pin is used to temporarily pause serial communication without deselecting or resetting the device. While the HOLD pin is asserted, transitions on the SCK pin and data on the SI pin will be ignored, and the SO pin will be in a high-impedance state. The CS pin must be asserted, and the SCK pin must be in the low state in order for a Hold condition to start. A Hold condition pauses serial communication only and does not have an effect on internally self-timed operations such as a program or erase cycle. Please refer to section “Hold” on page 30 for additional details on the Hold operation. The HOLD pin is internally pulled-high and may be left floating if the Hold function will not be used. However, it is recommended that the HOLD pin also be externally connected to VCC whenever possible. DEVICE POWER SUPPLY The VCC pin is used to supply the source voltage to the device. Operations at invalid VCC voltages may produce spurious results and should not be attempted. GROUND The ground reference for the power supply. GND should be connected to the system ground. Asserted State Type Input Input Output Input Input Power Figure 8-SOIC Top View CS 1 SO 2 WP 3 GND 4 8 VCC 7 HOLD 6 SCK 5 SI Ordering Information Green Package Options Pb/Halide-free/RoHS Compliant fSCK MHz Ordering Code Package AT26DF161A-SSU AT26DF161A-SU AT26DF161A-MU 8M1-A Operation Range Industrial -40°C to 85°C 8S1 8S2 8M1-A Package Type 8-lead, Wide, Plastic Gull Wing Small Outline Package JEDEC SOIC 8-lead, Wide, Plastic Gull Wing Small Outline Package EIAJ SOIC 8-pad, 6 x 5 x mm Very Thin Micro Lead-frame Package MLF 36 AT26DF161A Packaging Information 8S1 JEDEC SOIC AT26DF161A TOP VIEW SIDE VIEW END VIEW COMMON DIMENSIONS Unit of Measure = mm MIN NOM MAX NOTE Note These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TITLE 8S1, 8-lead Wide Body , Plastic Gull Wing Small Outline JEDEC SOIC 3/17/05 8S2 EIAJ SOIC TOP VIEW END VIEW COMMON DIMENSIONS Unit of Measure = mm SYMBOL MIN NOM MAX NOTE SIDE VIEW Notes This drawing is for general information only refer to EIAJ Drawing EDR-7320 for additional information. Mismatch of the upper and lower dies and resin burrs aren't included. Determines the true geometric position. Values b,C apply to plated terminal. The standard thickness of the plating layer shall measure between to mm. TITLE Package Drawing Contact 8S2, 8-lead, Body, Plastic Small Outline Package EIAJ 38 AT26DF161A 8M1-A MLF AT26DF161A Pin 1 ID E SIDE VIEW y TOP VIEW Pin #1 Notch R

PDF Datasheet Preview

• Single 2.7V - 3.6V Supply
• Serial Peripheral Interface SPI Compatible

Supports SPI Modes 0 and 3
• 70 MHz Maximum Clock Frequency
• Flexible, Uniform Erase Architecture
4-Kbyte Blocks 32-Kbyte Blocks 64-Kbyte Blocks Full Chip Erase
• Individual Sector Protection with Global Protect/Unprotect Feature Thirty-two 64-Kbyte Physical Sectors
• Hardware Controlled Locking of Protected Sectors
• Flexible Programming Options Byte/Page Program 1 to 256 Bytes Sequential Program Mode Capability
• Automatic Checking and Reporting of Erase/Program Failures
• JEDEC Standard Manufacturer and Device ID Read Methodology
• Low Power Dissipation 5 mA Active Read Current Typical 10 µA Deep Power-down Current Typical
• Endurance 100,000 Program/Erase Cycles
• Data Retention 20 Years
• Complies with Full Industrial Temperature Range
• Industry Standard Green Pb/Halide-free/RoHS Compliant Package Options 8-lead SOIC 150-mil and 208-mil wide 8-pad MLF 6 x 5 x mm
16-megabit 2.7-volt Only Serial Firmware Memory

AT26DF161A

For New Designs Use AT25DF161

The AT26DF161A is a serial interface Flash memory device designed for use in a wide variety of high-volume consumer-based applications in which program code is shadowed from Flash memory into embedded or external RAM for execution. The flexible erase architecture of the AT26DF161A, with its erase granularity as small as 4 Kbytes, makes it ideal for data storage as well, eliminating the need for additional data storage EEPROM devices.

The physical sectoring and the erase block sizes of the AT26DF161A have been optimized to meet the needs of today’s code and data storage applications. By optimizing the size of the physical sectors and erase blocks, the memory space can be used much more efficiently. Because certain code modules and data storage segments must reside by themselves in their own protected sectors, the wasted and unused memory space that occurs with large sectored and large block erase Flash memory devices can be greatly reduced. This increased memory space efficiency allows additional code routines and data storage segments to be added while still maintaining the same overall device density.

The AT26DF161A also offers a sophisticated method for protecting individual sectors against erroneous or malicious program and erase operations. By providing the ability to individually protect and unprotect sectors, a system can unprotect a specific sector to modify its contents while keeping the remaining sectors of the memory array securely protected. This is useful in applications where program code is patched or updated on a subroutine or module basis, or in applications where data storage segments need to be modified without running the risk of errant modifications to the program code segments. In addition to individual sector protection capabilities, the AT26DF161A incorporates Global Protect and Global Unprotect features that allow the entire memory array to be either protected or unprotected all at once. This reduces overhead during the manufacturing process since sectors do not have to be unprotected one-by-one prior to initial programming.

Specifically designed for use in 3-volt systems, the AT26DF161A supports read, program, and erase operations with a supply voltage range of 2.7V to 3.6V. No separate voltage is required for programming and erasing.
2 AT26DF161A

AT26DF161A

Pin Descriptions and Pinouts

Table Pin Descriptions

Symbol CS

SCK SI SO WP

HOLD

VCC GND

Name and Function

CHIP SELECT Asserting the CS pin selects the device. When the CS pin is deasserted, the device will be deselected and normally be placed in standby mode not Deep Power-down mode , and the SO pin will be in a high-impedance state. When the device is deselected, data will not be accepted on the SI pin.

A high-to-low transition on the CS pin is required to start an operation, and a low-to-high transition is required to end an operation. When ending an internally self-timed operation such as a program or erase cycle, the device will not enter the standby mode until the completion of the operation.

SERIAL CLOCK This pin is used to provide a clock to the device and is used to control the flow of data to and from the device. Command, address, and input data present on the SI pin is always latched on the rising edge of SCK, while output data on the SO pin is always clocked out on the falling edge of SCK.

SERIAL INPUT The SI pin is used to shift data into the device. The SI pin is used for all data input including command and address sequences. Data on the SI pin is always latched on the rising edge of SCK.

SERIAL OUTPUT The SO pin is used to shift data out from the device. Data on the SO pin is always clocked out on the falling edge of SCK.

WRITE PROTECT The WP pin controls the hardware locking feature of the device. Please refer to section “Protection Commands and Features” on page 15 for more details on protection features and the WP pin.

The WP pin is internally pulled-high and may be left floating if hardware-controlled protection will not be used. However, it is recommended that the WP pin also be externally connected to VCC whenever possible.

HOLD The HOLD pin is used to temporarily pause serial communication without deselecting or resetting the device. While the HOLD pin is asserted, transitions on the SCK pin and data on the SI pin will be ignored, and the SO pin will be in a high-impedance state.

The CS pin must be asserted, and the SCK pin must be in the low state in order for a Hold condition to start. A Hold condition pauses serial communication only and does not have an effect on internally self-timed operations such as a program or erase cycle. Please refer to section “Hold” on page 30 for additional details on the Hold operation.

The HOLD pin is internally pulled-high and may be left floating if the Hold function will not be used. However, it is recommended that the HOLD pin also be externally connected to VCC whenever possible.

DEVICE POWER SUPPLY The VCC pin is used to supply the source voltage to the device. Operations at invalid VCC voltages may produce spurious results and should not be attempted.

GROUND The ground reference for the power supply. GND should be connected to the system ground.

Asserted State

Type

Input

Input Output

Input

Input

Power

Figure 8-SOIC Top View

CS 1 SO 2 WP 3 GND 4
8 VCC 7 HOLD 6 SCK 5 SI
Ordering Information

Green Package Options Pb/Halide-free/RoHS Compliant
fSCK MHz
Ordering Code

Package

AT26DF161A-SSU

AT26DF161A-SU

AT26DF161A-MU
8M1-A

Operation Range

Industrial -40°C to 85°C
8S1 8S2 8M1-A

Package Type 8-lead, Wide, Plastic Gull Wing Small Outline Package JEDEC SOIC 8-lead, Wide, Plastic Gull Wing Small Outline Package EIAJ SOIC 8-pad, 6 x 5 x mm Very Thin Micro Lead-frame Package MLF
36 AT26DF161A

Packaging Information
8S1 JEDEC SOIC

AT26DF161A

TOP VIEW

SIDE VIEW

END VIEW

COMMON DIMENSIONS Unit of Measure = mm

MIN NOM MAX

NOTE

Note These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.
1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906

TITLE 8S1, 8-lead Wide Body , Plastic Gull Wing

Small Outline JEDEC SOIC
3/17/05
8S2 EIAJ SOIC

TOP VIEW

END VIEW

COMMON DIMENSIONS

Unit of Measure = mm

SYMBOL MIN NOM MAX NOTE

SIDE VIEW

Notes This drawing is for general information only refer to EIAJ Drawing EDR-7320 for additional information. Mismatch of the upper and lower dies and resin burrs aren't included. Determines the true geometric position. Values b,C apply to plated terminal. The standard thickness of the plating layer shall measure between to mm.

TITLE Package Drawing Contact 8S2, 8-lead, Body, Plastic Small Outline Package EIAJ
38 AT26DF161A
8M1-A MLF

AT26DF161A

Pin 1 ID E

SIDE VIEW y

TOP VIEW

Pin #1 Notch R

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Datasheet ID: AT26DF161A-SU 515445